NEC V850E/MS1 UPD703100, User Manual

Page: 252 / 449

CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
User’s Manual U12688EJ4V0UM00
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(2) Capture/compare registers 1n0 to 1n3 (CC1n0 to CC1n3) (n = 0 to 5)
The capture/compare registers are 16-bit registers to which TM1n is connected. They can be used as either
a capture register or a compare register in accordance with the specification in timer unit mode register 1n
(TUM1n). These registers can be read/written in 16-bit units.
CC110 to
CC113
FFFFF272H to
FFFFF278H
Undefined
CC120 to
CC123
FFFFF292H to
FFFFF298H
Undefined
15
CC100 to
CC103
Address
FFFFF252H to
FFFFF258H
After reset
Undefined
0
CC130 to
CC133
FFFFF2B2H to
FFFFF2B8H
Undefined
CC140 to
CC143
FFFFF2D2H to
FFFFF2D8H
Undefined
CC150 to
CC153
FFFFF2F2H to
FFFFF2F8H
Undefined
(a) Set as a capture register
If set as a capture register, these registers detect the active edge of the corresponding signals in external
interrupts INTP1n0 to INTP1n3 as a capture trigger. Timer 1n is synchronized with the capture trigger
and latches a count value (capture operation). The capture operation is performed out of synch with the
count clock. The latched value is held in the capture register until the next capture operation is
performed.
If the capture (latch) timing to the capture register and writing to the register in response to an instruction
are in contention, the latter has the priority and the capture operation is disregarded.
Also, specification of the active edge of external interrupts (rising, falling, or both edges) can be selected
by the external interrupt mode register (INTM1 to INTM6).
When there is a specification in the capture register, an interrupt is issued when the active edge of
INTP1n0 to INTP1n3 signals is detected. When this is done, an interrupt cannot be issued by INTCC1n0
to INTCC1n3, which are the compare register’s matching signals.
(b) Set as a compare register
If set as a compare register, these registers perform a comparison of the timer and register values at
each count clock of the timer, and issue an interrupt if the values match.
The compare registers are provided with a set/reset output function. In synch with matching signal
generation, the corresponding timer output (TO1n0, TO1n1) is set or reset.
The interrupt source differs with the function of the register.
If specified a compare register, these registers can be made interrupt signals by selecting, through the
specification of the TUM1n register, active edge detection of either the INTCC1n0 to INTCC1n3 signals,
which are the matching signals, or the INTP1n0 to INTP1n3 signals.
Furthermore, if the INTP1n0 to INTP1n3 signals are selected, acknowledgement of an external interrupt
request and timer output by the compare register’s set/reset output function can be carried out in parallel.