NEC V850E/MS1 UPD703100 User Manual Download Page 308

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CHAPTER 10 SERIAL INTERFACE FUNCTION

User’s Manual U12688EJ4V0UM00

308

10.3.7 Transmission and reception by CSI0 to CSI3

If both transmission and reception by clocked serial interface mode register n (CSIMn) are enabled, transmit and

receive operations can be carried out simultaneously (n = 0 to 3).

(1) Starting transmit and receive operations

When both the CTXEn bit and CRXEn bit of clocked serial interface mode register n (CSIMn) are set (1), both

transmit operations and receive operations can be performed simultaneously (transmit/receive operations).

Transmit and receive operations are started when both the CTXEn and CRXEn bits of the CSIMn register are

set to 1, enabling transmission and reception and when transmit data is written to shift register n (SIOn).

If the CRXEn bit of the CSIMn register is 1, even if data is written again, a transmit/receive operation is not

started.

(2) Transmitting data in synchronization with the serial clock

(a) If the internal clock is selected as the serial clock

When transmission/reception is started, the serial clock is output from the SCKn pin and at the same time,

data from the SIOn register is output sequentially to the SOn pin in synchronization with the fall of the

serial clock. Also, data from the SIn pin is fetched sequentially to the SIOn register in synchronization

with the rise of the serial clock.

(b) If an external clock is selected as the serial clock

When transmission/reception is started, data from the SIOn register is output sequentially to the SOn pin

in synchronization with the fall of the serial clock input to the SCKn pin after transmission/reception starts.

Also, data from the SIn pin is fetched sequentially to the SIOn register in synchronization with the rise of

the serial clock. When transmission/reception is not started, even if the serial clock is input to the SCKn

pin, shift operations are not performed and the output level of the SOn pin does not change.

Summary of Contents for V850E/MS1 UPD703100

Page 1: ... µPD703101 µ µ µ µPD703101A µ µ µ µPD703102 µ µ µ µPD703102A µ µ µ µPD70F3102 µ µ µ µPD70F3102A Printed in Japan Document No U12688EJ4V0UM00 4th edition Date Published January 2000 N CP K V850E MS1 TM 32 16 Bit Single Chip Microcontrollers Hardware 1997 ...

Page 2: ...User s Manual U12688EJ4V0UM00 2 MEMO ...

Page 3: ... to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an...

Page 4: ... assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect ...

Page 5: ...esseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58...

Page 6: ...User s Manual U12688EJ4V0UM00 6 MEMO ...

Page 7: ...6 Modification of Figure 11 3 Select Mode Operation Timing 1 Buffer Mode ANI1 p 349 Change of block type of Port 2 in 12 2 1 Function of each port p 355 Modification of Figure 12 3 Type C Block Diagram p 367 Addition of Figure 12 17 Type Q Block Diagram p 374 Change of block types of P22 and P25 in 12 3 3 1 Operation in control mode p 375 Modification of Caution in 12 3 3 2 a Port 2 mode register ...

Page 8: ...User s Manual U12688EJ4V0UM00 8 MEMO ...

Page 9: ...ware Architecture Pin functions Data type CPU function Register set Internal peripheral functions Instruction format and instruction set Flash memory programming Interrupts and exceptions Pipeline operation How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To find the details of a register wher...

Page 10: ...the top and lower address on the bottom Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefix indicating power of 2 address space memory K kilo 2 10 1 024 capacity M mega 2 20 1 024 2 G giga 2 30 1 024 3 Data type Word 32 bits Halfwor...

Page 11: ...anuals Document Name Document No IE 703102 MC In circuit Emulator U13875E IE 703102 MC EM1 IE 703102 MC EM1 A In circuit Emulator Option Board U13876E Operation U13998E C Language U13997E Assembly Language U13828E CA850 C Compiler Package Project Manager U13996E Basics U13430E RX850 Real Time OS Installation U13410E Fundamental U13773E RX850 Pro Real Time OS Installation U13774E ID850 Integrated D...

Page 12: ...User s Manual U12688EJ4V0UM00 12 MEMO ...

Page 13: ...Features 69 3 2 CPU Register Set 70 3 2 1 Program register set 71 3 2 2 System register set 72 3 3 Operation Modes 74 3 3 1 Operation modes 74 3 3 2 Operation mode specification 75 3 4 Address Space 76 3 4 1 CPU address space 76 3 4 2 Image 77 3 4 3 Wrap around of CPU address space 78 3 4 4 Memory map 79 3 4 5 Area 80 3 4 6 External expansion mode 87 3 4 7 Recommended use of address space 89 3 4 8...

Page 14: ...ess 126 5 2 Page ROM Controller ROMC 130 5 2 1 Features 130 5 2 2 Page ROM connections 130 5 2 3 On page off page judgment 132 5 2 4 Page ROM configuration register PRC 134 5 2 5 Page ROM access 135 5 3 DRAM Controller 136 5 3 1 Features 136 5 3 2 DRAM connections 137 5 3 3 Address multiplex function 138 5 3 4 DRAM configuration registers 0 to 3 DRC0 to DRC3 139 5 3 5 DRAM type configuration regis...

Page 15: ...er Start Factors 191 6 11 Interrupting DMA Transfer 192 6 11 1 Interruption factors 192 6 11 2 Forcible interruption 192 6 12 Terminating DMA Transfer 192 6 12 1 DMA transfer end interrupt 192 6 12 2 Terminal count output 192 6 12 3 Forcible termination 193 6 13 Boundary of Memory Area 194 6 14 Transfer of Misalign Data 194 6 15 Clocks of DMA Transfer 194 6 16 Maximum Response Time to DMA Request ...

Page 16: ...ection 232 8 3 1 Direct mode 232 8 3 2 PLL mode 232 8 3 3 Clock control register CKC 233 8 4 PLL Lockup 234 8 5 Power Saving Control 235 8 5 1 Outline 235 8 5 2 Control registers 237 8 5 3 HALT mode 238 8 5 4 IDLE mode 240 8 5 5 Software STOP mode 242 8 5 6 Clock output inhibit mode 243 8 6 Securing Oscillation Stabilization Time 244 8 6 1 Specifying securing of oscillation stabilization time 244 ...

Page 17: ... 8 Example of system configuration 309 10 4 Dedicated Baud Rate Generators 0 to 2 BRG0 to BRG2 310 10 4 1 Configuration and function 310 10 4 2 Baud rate generator compare registers 0 to 2 BRGC0 to BRGC2 313 10 4 3 Baud rate generator prescaler mode registers 0 to 2 BPRM0 to BPRM2 314 CHAPTER 11 A D CONVERTER 315 11 1 Features 315 11 2 Configuration 315 11 3 Control Registers 318 11 4 A D Converte...

Page 18: ... 3 10 Port 9 391 12 3 11 Port 10 394 12 3 12 Port 11 397 12 3 13 Port 12 401 12 3 14 Port A 403 12 3 15 Port B 405 12 3 16 Port X 407 CHAPTER 13 RESET FUNCTIONS 409 13 1 Features 409 13 2 Pin Functions 409 13 3 Initialization 410 CHAPTER 14 FLASH MEMORY µ µ µ µPD70F3102 70F3102A 413 14 1 Features 413 14 2 Writing by Flash Programmer 413 14 3 Programming Environment 414 14 4 Communication System 41...

Page 19: ...programming mode 419 14 6 3 Selection of communication mode 419 14 6 4 Communication command 420 APPENDIX A REGISTER INDEX 423 APPENDIX B INSTRUCTION SET LIST 431 B 1 General Examples 431 B 2 Instruction Set in Alphabetical Order 434 APPENDIX C INDEX 441 ...

Page 20: ...132 5 5 Page ROM Access Timing 135 5 6 Examples of Connections to DRAM 137 5 7 Row Address Column Address Output 138 5 8 High Speed Page DRAM Access Timing 143 5 9 EDO DRAM Access Timing 147 5 10 DRAM Access Timing During DMA Flyby Transfer 151 5 11 CBR Refresh Timing 157 5 12 CBR Self Refresh Timing 159 6 1 DMAC Bus Cycle State Transition Diagram 178 6 2 Single Transfer Example 1 179 6 3 Single T...

Page 21: ...ssing 223 7 12 Exception Trap Processing 226 7 13 Pipeline Operation at Interrupt Request Acknowledgement Outline 229 8 1 Power Save Mode State Transition Diagram 236 9 1 Basic Operation of Timer 1 262 9 2 Operation after Overflow If ECLR1n 0 and OSTn 1 264 9 3 Timer Clear Start Operation by TCLR1n Signal Input If ECLR1n 1 and OSTn 0 265 9 4 Relationship Between Clear Start by TCLR1n Signal Input ...

Page 22: ...ocked Serial Interface 300 10 7 Timing of 3 Wire Serial I O Mode Transmission 306 10 8 Timing of 3 Wire Serial I O Mode Reception 307 10 9 Timing of 3 Wire Serial I O Mode Transmission Reception 309 10 10 Example of CSI System Configuration 309 10 11 Block Diagram of Dedicated Baud Rate Generator 310 11 1 A D Converter Block Diagram 317 11 2 Relationship Between Analog Input Voltage and A D Conver...

Page 23: ...ernal Trigger Scan Operation 344 11 18 Relationship of A D Converter and Port INTC and RPU 346 12 1 Type A Block Diagram 353 12 2 Type B Block Diagram 354 12 3 Type C Block Diagram 355 12 4 Type D Block Diagram 356 12 5 Type E Block Diagram 357 12 6 Type F Block Diagram 358 12 7 Type G Block Diagram 358 12 8 Type H Block Diagram 359 12 9 Type I Block Diagram 359 12 10 Type J Block Diagram 360 12 1...

Page 24: ...n DMA Cycle 194 6 4 DMAAKn Active DMARQn Inactive Time for Single Transfer to External Memory 196 7 1 Interrupt List 200 7 2 Interrupt Control Register Addresses and Bits 216 8 1 Clock Generator Operation by Power Save Control 236 8 2 Operating States When in HALT Mode 238 8 3 Operations after HALT Mode Is Released by Interrupt Request 239 8 4 Operating States When in IDLE Mode 240 8 5 Operating S...

Page 25: ...EJ4V0UM00 25 LIST OF TABLES 2 2 Table No Title Page 13 1 Operating State of Each Pin During Reset 409 13 2 Initial Values of CPU Internal RAM and Internal Peripheral I O after Reset 411 14 1 List of Communication Modes 419 ...

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Page 27: ... chip external memory interfaces including separately address configured 24 bits and data 16 bits buses and SRAM and ROM interfaces as well as on chip memory controllers that can be directly linked to EDO DRAM high speed page DRAM page ROM etc thereby raising the system performance and reducing the number of parts needed for application systems Also through the DMA controller CPU internal calculat...

Page 28: ...32 MB linear address space common program data use Chip select output function 8 spaces Memory block division function 2 4 8 MB block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data multiplexed 16 8 bit bus sizing function Bus hold function External wait function Part Number Internal ROM Internal RAM µPD703100 703100A None 4 Kbytes µPD70...

Page 29: ...bit timers 6 16 bit capture compare registers 24 16 bit interval timer 2 channels Serial interface Asynchronous serial interface UART Clocked serial interface CSI UART CSI 2 channels CSI 2 channels Dedicated baud rate generator 3 channels A D converter 10 bit resolution A D converter 8 channels Clock generator A multiply by five function via a PLL clock synthesizer A divide by two function via ext...

Page 30: ...EU Note 144 pin plastic LQFP Fine pitch 33 MHz None 4 5 to 5 5 V 20 20 mm µPD703101AF1 33 FA1 Note 157 pin plastic FBGA 33 MHz Mask ROM 3 0 to 3 6 V 14 14 mm 96 KB µPD703101AGJ 33 8EU 144 pin plastic LQFP Fine pitch 33 MHz Mask ROM 3 0 to 3 6 V 20 20 mm 96 KB µPD703101GJ 33 8EU Note 144 pin plastic LQFP Fine pitch 33 MHz Mask ROM 4 5 to 5 5 V 20 20 mm 96 KB µPD703102AF1 33 FA1 Note 157 pin plastic...

Page 31: ... Number Pin Name Pin Number Pin Name Pin Number Pin Name A1 B1 INTP103 DMARQ3 P07 C1 INTP101 DMARQ1 P05 A2 D0 P40 B2 D1 P41 C2 INTP102 DMARQ2 P06 A3 D2 P42 B3 D3 P43 C3 VSS A4 D4 P44 B4 D5 P45 C4 VSS A5 D6 P46 B5 D7 P47 C5 HVDD A6 D8 P50 B6 D9 P51 C6 VSS A7 D10 P52 B7 D11 P53 C7 D12 P54 A8 D13 P55 B8 D14 P56 C8 D15 P57 A9 A0 PA0 B9 A1 PA1 C9 HVDD A10 A2 PA2 B10 A3 PA3 C10 A4 PA4 A11 A5 PA5 B11 A6 ...

Page 32: ...14 MODE2 F15 CS1 RAS1 P81 M16 CLKOUT PX7 R15 INTP153 ADTRG P127 F16 CS0 RAS0 P80 N1 ANI2 P72 R16 INTP152 P126 G1 INTP110 DMAAK0 P14 N2 ANI3 P73 T1 G2 INTP111 DMAAK1 P15 N3 ANI4 P74 T2 AVREF G3 INTP112 DMAAK2 P16 N14 TI15 P123 T3 NMI P20 G14 CS5 RAS5 IORD P85 N15 TCLR15 P122 T4 RXD0 SI0 P23 G15 CS4 RAS4 IOWR P84 N16 TO151 P121 T5 RXD1 SI1 P26 G16 CS3 RAS3 P83 P1 AVDD T6 INTP131 SO2 P35 H1 TO111 P11...

Page 33: ...CLR15 P122 TI15 P123 INTP150 P124 INTP151 P125 INTP152 P126 NMI P20 P21 TXD0 SO0 P22 RXD0 SI0 P23 SCK0 P24 TXD1 SO1 P25 RXD1 SI1 P26 SCK1 P27 V DD INTP133 SCK2 P37 INTP132 SI2 P36 INTP131 SO2 P35 INTP130 P34 TI13 P33 TCLR13 P32 TO131 P31 TO130 P30 INTP143 SCK3 P117 INTP142 SI3 P116 INTP141 SO3 P115 INTP140 P114 TI14 P113 TCLR14 P112 TO141 P111 TO140 P110 CV DD X2 X1 CV SS CKSEL MODE0 MODE1 MODE2 M...

Page 34: ...for External Pins Interrupt Request from Peripherals I O Read Strobe I O Write Strobe Lower Column Address Strobe Lower Write Strobe Mode Non Maskable Interrupt Request Output Enable Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127 PA0 to PA7 PB0 to PB7 PX5 to PX7 RAS0 to RAS7 RD REFRQ RESET RXD0 RXD1 SCK0 to SCK3 SI0 to S...

Page 35: ...110 to P117 P100 to P107 P90 to P97 P80 to P87 P70 to P77 P60 to P67 P50 to P57 P40 to P47 P30 to P37 P21 to P27 P20 P10 to P17 P00 to P07 HV DD CG System controller BCU HLDRQ HLDAK CS0 to CS7 RAS0 to RAS7 IOWR IORD REFRQ BCYST WE RD OE UWR UCAS LWR LCAS WAIT A0 to A23 D0 to D15 DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3 CLKOUT CKSEL X1 X2 CVDD CVSS MODE0 to MODE3 RESET VPP UART0 CSI0 BRG0 UART1...

Page 36: ... normal access off page and page access on page Also it includes a refresh function that is compatible with the CBR refresh cycle b Page ROM controller This controller is compatible with ROM that includes a page access function It performs address comparisons with the immediately preceding bus cycle and executes wait control for normal access off page page access on page It can handle page widths ...

Page 37: ... and X2 only when an internal PLL synthesizer is used or an external clock is input from pin X1 7 Real time pulse unit RPU This unit has a 6 channel 16 bit timer event counter and 2 channel 16 bit interval timer on chip and it is possible to measure pulse widths or frequency and to output a programmable pulse 8 Serial interface SIO The serial interface has a total of 4 channels of asynchronous ser...

Page 38: ...8 bit I O External data bus Port 5 8 bit I O External data bus Port 6 8 bit I O External address bus Port 7 8 bit input A D converter input Port 8 8 bit I O External bus interface control signal output Port 9 8 bit I O External bus interface control signal input output Port 10 8 bit I O Real time pulse unit input output external interrupt input DMA controller output Port 11 8 bit I O Real time pul...

Page 39: ... output port Input output mode can be specified in 1 bit units INTP103 DMARQ3 P10 TO110 P11 TO111 P12 TCLR11 P13 TI11 P14 INTP110 DMAAK0 P15 INTP111 DMAAK1 P16 INTP112 DMAAK2 P17 I O Port 1 8 bit input output port Input output mode can be specified in 1 bit units INTP113 DMAAK3 P20 Input NMI P21 P22 TXD0 SO0 P23 RXD0 SI0 P24 SCK0 P25 TXD1 SO1 P26 RXD1 SI1 P27 I O Port 2 P20 is an input only port I...

Page 40: ...O Port 5 8 bit input output port Input output mode can be specified in 1 bit units D8 to D15 P60 to P67 I O Port 6 8 bit input output port Input output mode can be specified in 1 bit units A16 to A23 P70 to P77 Input Port 7 8 bit input only port ANI0 to ANI7 P80 CS0 RAS0 P81 CS1 RAS1 P82 CS2 RAS2 P83 CS3 RAS3 P84 CS4 RAS4 IOWR P85 CS5 RAS5 IORD P86 CS6 RAS6 P87 I O Port 8 8 bit input output port I...

Page 41: ...TO140 P111 TO141 P112 TCLR14 P113 TI14 P114 INTP140 P115 INTP141 SO3 P116 INTP142 SI3 P117 I O Port 11 8 bit input output port Input output mode can be specified in 1 bit units INTP143 SCK3 P120 TO150 P121 TO151 P122 TCLR15 P123 TI15 P124 INTP150 P125 INTP151 P126 INTP152 P127 I O Port 12 8 bit input output port Input output mode can be specified in 1 bit units INTP153 ADTRG PA0 A0 PA1 A1 PA2 A2 P...

Page 42: ... Function Alternate Function PB0 A8 PB1 A9 PB2 A10 PB3 A11 PB4 A12 PB5 A13 PB6 A14 PB7 I O Port B 8 bit input out port Input output mode can be specified in 1 bit units A15 PX5 REFRQ PX6 WAIT PX7 I O Port X 3 bit input output port Input output mode can be specified in 1 bit units CLKOUT ...

Page 43: ... P122 TI10 P03 TI11 P13 TI12 P103 TI13 P33 TI14 P113 TI15 Input External count clock input of timers 10 to 15 P123 INTP100 P04 DMARQ0 INTP101 P05 DMARQ1 INTP102 P06 DMARQ2 INTP103 Input External maskable interrupt request input or timer 10 external capture trigger input P07 DMARQ3 INTP110 P14 DMAAK0 INTP111 P15 DMAAK1 INTP112 P16 DMAAK2 INTP113 Input External maskable interrupt request input or ti...

Page 44: ...to CSI3 serial transmission data output 3 wire P115 INTP141 SI0 P23 RXD0 SI1 P26 RXD1 SI2 P36 INTP132 SI3 Input CSI0 to CSI3 serial reception data input 3 wire P116 INTP142 SCK0 P24 SCK1 P27 SCK2 P37 INTP133 SCK3 I O CSI0 to CSI3 serial clock input output 3 wire P117 INTP143 TXD0 P22 SO0 TXD1 Output UART0 and UART1 serial transmission data output P25 SO1 RXD0 P23 SI0 RXD1 Input UART0 and UART1 ser...

Page 45: ...ut P87 RAS7 WAIT Input Control signal input that inserts a wait in the bus cycle PX6 REFRQ Output Refresh request signal output for DRAM PX5 IOWR Output DMA write strobe signal output P84 RAS4 CS4 IORD Output DMA read strobe signal output P85 RAS5 CS5 DMARQ0 to DMARQ3 Input DMA request signal input P04 INTP100 to P07 INTP103 DMAAK0 to DMAAK3 Output DMA acknowledge signal output P14 INTP110 to P17 ...

Page 46: ... INTP153 AVREF Input Reference voltage applied to A D converter AVDD Positive power supply to A D converter AVSS Ground for A D converter CVDD Supplies a positive power supply for the dedicated clock generator CVSS Ground potential for the dedicated clock generator VDD Supplies the positive power supply internal unit power supply HVDD Supplies the positive power supply external pin power supply VS...

Page 47: ...ng Operating HLDAK Hi Z Hi Z Hi Z Operating L Operating WAIT Operating CLKOUT Note 1 L L Operating Operating Operating DMARQ0 to DMARQ3 Operating Operating Operating DMAAK0 to DMAAK3 Hi Z H H Operating H H TC0 to TC3 Hi Z H H Operating Operating Operating INTP100 to INTP103 INTP110 to INTP113 INTP120 to INTP123 INTP130 to INTP133 INTP140 to INTP143 INTP150 to INTP153 Operating Operating Operating ...

Page 48: ...cycle is held H High level output L Low level output No sampling of input Cautions when turning on off power supply The V850E MS1 is configured with two power supply pins the internal unit power supply pin VDD and the external pin power supply pin HVDD If the voltage exceeds its operation guaranteed range the input output state of the I O pins may become undefined If this input output undefined st...

Page 49: ...ontrol mode P00 to P07 can be set in the port control mode in bit units by the PMC0 register i TO100 TO101 Timer Output output Output the pulse signals for timer 1 ii TCLR10 Timer Clear input This is an input pin for external clear signals for timer 1 iii TI10 Timer Input input This is an input pin for an external counter clock for timer 1 iv INTP100 to INTP103 Interrupt Request from Peripherals i...

Page 50: ...put Output the pulse signals for timer 1 ii TCLR11 Timer Clear input This is an input pin for external clear signals for timer 1 iii TI11 Timer Input input This is an input pin for an external counter clock for timer 1 iv INTP110 to INTP113 Interrupt Request from Peripherals input These are input pins for external interrupt requests for timer 1 v DMAAK0 to DMAAK3 DMA Acknowledge output This signal...

Page 51: ... in bit units by the port 2 mode register PM2 P20 is an exclusive input port and if a valid edge is input it operates as an NMI input b Control mode P22 to P27 can be set in the port control mode in bit units by the PMC2 register i NMI Non Maskable Interrupt Request input This is the input pin for non maskable interrupt requests ii TXD0 TXD1 Transmit Data output Output UART0 UART1 serial transmit ...

Page 52: ...tput in bit units by the port 3 mode register PM3 b Control mode P30 to P37 can be set in the port control mode in bit units by the PMC3 register i TO130 TO131 Timer Output output Output pulse signals for timer 1 ii TCLR13 Timer Clear input This is an input pin for external clear signals for timer 1 iii TI13 Timer Input input This is an input pin for an external counter clock for timer 1 iv INTP13...

Page 53: ...with the falling of the clock in the T1 state CLKOUT signal of the bus cycle In the idle state TI the impedance becomes high 6 P50 to P57 Port 5 3 state I O Port 5 is an 8 bit input output port that can be set to input or output in 1 bit units Besides functioning as an I O port in the control mode external expansion mode it operates as a data bus D8 to D15 when memory is externally expanded The op...

Page 54: ...d The output changes in synchronization with the falling edge of the CLKOUT signal in the T1 state of the bus cycle In the idle state TI the previous bus cycle s address is held 8 P70 to P77 Port 7 input Port 7 is an 8 bit input only port in which all pins are fixed as input pins Besides functioning as a port in the control mode it operates as analog input for the A D converter However the input p...

Page 55: ...le when the corresponding memory block is accessed starts In the idle state TI it becomes inactive ii RAS0 to RAS7 Row Address Strobe 3 state output This is the strobe signal for the row address for the DRAM area and the strobe signal for the CBR refresh cycle The RASn signal is assigned to memory block n n 0 to 7 During on page disable after the DRAM access bus cycle ends it becomes inactive Duri...

Page 56: ... in the port control mode in bit units by the PMC9 register i LCAS Lower Column Address Strobe 3 state output This is the strobe signal for column address for DRAM and the strobe signal for the CBR refresh cycle In the data bus the lower byte is valid ii UCAS Upper Column Address Strobe 3 state output This is the strobe signal for column address for DRAM and the strobe signal for the CBR refresh c...

Page 57: ...e state TI it becomes inactive ix HLDAK Hold Acknowledge output In this mode this pin is the output pin for the acknowledge signal that indicates high impedance status for the address bus data bus and control bus when the V850E MS1 receives a bus hold request While this signal is active the impedance of the address bus data bus and control bus becomes high and the bus mastership is transferred to ...

Page 58: ... be set to input or output in bit units by the port 10 mode register PM10 b Control mode P100 to P107 can be set in the port control mode in bit units by the PMC10 register i TO120 TO121 Timer Output output Output the pulse signal of timer 1 ii TCLR12 Timer Clear input This is an input pin for external clear signals for timer 1 iii TI12 Timer Input input This is an input pin for an external counte...

Page 59: ...bit units by the port 11 mode register PM11 b Control mode P110 to P117 can be set in the port control mode in bit units by the PMC11 register i TO140 TO141 Timer Output output Output the pulse signal of timer 1 ii TCLR14 Timer Clear input This is an input pin for external clear signals for timer 1 iii TI14 Timer Input input This is an input pin for an external counter clock for timer 1 iv INTP140...

Page 60: ...egister PMC12 a Port mode P120 to P127 can be set to input or output in bit units by the port 12 mode register PM12 b Control mode P120 to P127 can be set in the port control mode in bit units by the PMC12 register i TO150 TO151 Timer Output output Output the pulse signal of timer 1 ii TCLR15 Timer Clear input This is an input pin for external clear signals for timer 1 iii TI15 Timer Input input T...

Page 61: ...LKOUT signal in the T1 state of the bus cycle In the idle state TI the previous bus cycle s address is held 15 PB0 to PB7 Port B 3 state I O Port B is an 8 bit input output port that can be set to input or output in 1 bit units Besides functioning as a port in the control mode external expansion mode it operates as an address bus A8 to A15 when memory is externally expanded The operation mode can ...

Page 62: ...he refresh cycle This signal becomes active during the refresh cycle Also during bus hold it becomes active when a refresh request is generated and informs the external bus master that a refresh request was generated ii WAIT Wait input This is the control signal input pin that inserts a data wait in the bus cycle and it can be input asynchronously with respect to the CLKOUT signal When the CLKOUT ...

Page 63: ...ge during operation a µ µ µ µPD703100 703100A MODE3 MODE2 MODE1 MODE0 Operation Mode L L L L ROM less mode 0 L L L H Normal operation mode ROM less mode 1 Other than above Setting prohibited b µ µ µ µPD703101 703101A 703102 703102A MODE3 MODE2 MODE1 MODE0 Operation Mode L L L L ROM less mode 0 L L L H ROM less mode 1 L L H L Single chip mode 0 L L H H Normal operation mode Single chip mode 1 Other...

Page 64: ...positive power to the clock generator 22 CVSS Ground for Clock Generator This is the ground pin of the clock generator 23 VDD Power Supply for Internal Unit These are the positive power supply pins for each internal unit All the VDD pins should be connected to a positive power source 3 3 V 24 HVDD Power Supply for External Pins These are the positive power supply pins for external pins All the HVD...

Page 65: ...or VSS via a resistor Output Leave open P20 NMI 2 Connect directly to VSS P21 P22 TXD0 SO0 5 P23 RXD0 SI0 P24 SCK0 5 K P25 TXD1 SO1 5 P26 RXD1 SI1 P27 SCK1 5 K P30 TO130 P31 TO131 5 P32 TCLR13 P33 TI13 P34 INTP130 P35 INTP131 SO2 P36 INTP132 SI2 P37 INTP133 SCK2 5 K P40 D0 to P47 D7 P50 D8 to P57 D15 P60 A16 to P67 A23 5 Input Independently connect to HVDD or VSS via a resistor Output Leave open P...

Page 66: ...20 TO150 P121 TO151 5 P122 TCLR15 P123 TI15 P124 INTP150 to P126 INTP152 P127 INTP153 ADTRG 5 K PA0 A0 to PA7 A7 PB0 A8 to PB7 A15 PX5 REFRQ PX6 WAIT PX7 CLKOUT 5 Input Independently connect to HVDD or VSS via a resistor Output Leave open CKSEL 1 Connect directly to HVDD RESET MODE0 to MODE2 MODE3 Note 1 MODE3 VPP Note 2 2 Connect to VSS via a resistor RVPP AVREF AVSS Connect directly to VSS AVDD ...

Page 67: ...ch IN VDD IN Schmitt triggered input with hysteresis characteristics P ch N ch VDD IN OUT Data Output disable Input enable Type 5 K P ch N ch VDD IN OUT Data Output disable Input enable IN Comparator VREF threshold voltage P ch N ch Input enable Type 9 Caution Note that VDD in the circuit diagram is replaced by HVDD ...

Page 68: ...User s Manual U12688EJ4V0UM00 68 MEMO ...

Page 69: ...nternal 40 MHz operation µPD703100 40 703100A 40 30 ns at internal 33 MHz operation other than above Memory space Program space 64 MB Linear Data space 4 GB Linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction Long short instruction format ...

Page 70: ... r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Address Generation Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Exception Cause Register FEPC FEPSW Fatal Error PC Fatal Error PSW EIPC EIPSW Exception Interrupt P...

Page 71: ...erved register Working register for generating 32 bit immediate data r2 Interrupt stack pointer Stack pointer for interrupt handler r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text area where program code is located r6 to r29 Address data variable registers ...

Page 72: ...nterrupt is set Refer to Figure 3 2 5 PSW Program status word The program status word is a collection of flags that indicate the program status instruction execution result and CPU status Refer to Figure 3 3 16 CTPC 17 CTPSW Status saving register during CALLT execution If the CALLT instruction is executed this register saves the PC and PSW 18 DBPC 19 DBPSW Status saving register during exception ...

Page 73: ... be accepted when this bit is set 5 ID Interrupt Disable Indicates that accepting maskable interrupt request is disabled 4 SAT Saturated Math This flag is set if the result of executing saturated operation instruction overflows if overflow does not occur value of previous operation is held 3 CY Carry This flag is set if carry or borrow occurs as result of operation if carry or borrow does not occu...

Page 74: ...an instruction In single chip mode 1 after system reset is cancelled each pin related to the bus interface enters the control mode branches to the external device memory reset entry address and starts instruction processing The internal ROM area is mapped from address 100000H b ROM less modes 0 1 After system reset is cancelled each pin related to the bus interface enters the control mode branches...

Page 75: ...ODE0 Operation Mode External Data Bus Width Remarks L L L L ROM less mode 0 16 bits L L L H ROM less mode 1 8 bits L L H L Single chip mode 0 Internal ROM area is allocated from address 000000H L L H H Normal operation mode Single chip mode 1 16 bits Internal ROM area is allocated from address 100000H Other than above Setting prohibited c µ µ µ µPD70F3102 70F3102A MODE3 VPP MODE2 MODE1 MODE0 Opera...

Page 76: ...p to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 4 shows the CPU address space Figure 3 4 CPU Address Space FFFFFFFFH 04000000H 03FFFFFFH 00000000H Data area 4 GB linear Program area 64 MB linear CPU address space ...

Page 77: ...ace Because the higher 6 bits of a 32 bit CPU address are disregarded and access is made to a 26 bit physical address physical address x0000000H can be seen as CPU address 00000000H and in addition can be seen as address 04000000H address 08000000H address F8000000H or address FC000000H Figure 3 5 Image on Address Space FFFFFFFFH FC000000H FBFFFFFFH 00000000H Internal ROM Image Image Image Interna...

Page 78: ...upper limit address become contiguous like this Caution No instruction can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is defined as the peripheral I O area Therefore do not execute any branch address calculation in which the result will reside in any part of this area 03FFFFFEH 03FFFFFFH 00000000H 00000001H Program space Program space direction direction 2 Data space...

Page 79: ...al memory area External memory area External memory area Internal ROM area External memory area Reserved area Internal ROM area External memory area Single chip mode 0Note 1 Single chip mode 1Note 1 ROM less mode 0 1 16 Mbytes 32 Mbytes 16 Mbytes 1 Mbyte 1 Mbyte 4 Kbytes x3FFF000H x3FFEFFFH x1000000H x0FFFFFFH x0200000H x01FFFFFH x0100000H x00FFFFFH x0000000H x3FFE000H x3FFDFFFH x3000000H x2FFFFFF...

Page 80: ...µ µ µ µPD703101 703101A 96 KB of memory addresses 00000H to 17FFFH is provided as physical internal ROM mask ROM Also in the remaining area 20000H to FFFFFH the image of 00000H to 1FFFFH can be seen however addresses 18000H to 1FFFFH are fixed at 1 x00FFFFFH x00E0000H x00DFFFFH x0040000H x003FFFFH x0020000H x001FFFFH x0000000H Image Image Image Physical internal ROM Mask ROM 1FFFFH 18000H 17FFFH 0...

Page 81: ...00H to 1FFFFH is provided as physical internal ROM mask ROM Also in the remaining area 20000H to FFFFFH the image of 00000H to 1FFFFH can be seen x00FFFFFH x00E0000H x00DFFFFH x0040000H x003FFFFH x0020000H x001FFFFH x0000000H Image Image Image Physical internal ROM Mask ROM 1FFFFH 00000H Interrupt exception table ...

Page 82: ...upt response speed by assigning handler addresses corresponding to interrupts exceptions The collection of these handler addresses is called an interrupt exception table which is located in the internal ROM area When an interrupt exception request is granted execution jumps to the handler address and the program written at that memory is executed Table 3 3 shows the sources of interrupts exception...

Page 83: ...INTCC101 00000120H INTP102 INTCC102 00000130H INTP103 INTCC103 00000140H INTP110 INTCC110 00000150H INTP111 INTCC111 00000160H INTP112 INTCC112 00000170H INTP113 INTCC113 00000180H INTP120 INTCC120 00000190H INTP121 INTCC121 000001A0H INTP122 INTCC122 000001B0H INTP123 INTCC123 000001C0H INTP130 INTCC130 000001D0H INTP131 INTCC131 000001E0H INTP132 INTCC132 000001F0H INTP133 INTCC133 00000200H INT...

Page 84: ...R1 00000370H INTST1 00000380H INTCSI2 000003C0H INTCSI3 00000400H INTAD c Internal ROM area relocation function If set in single chip mode 1 the internal ROM area is located beginning from address 100000H so booting from external memory becomes possible Therefore in order to restore correct operation after reset provide a handler address to the reset routine in address 0 of the external memory Fig...

Page 85: ...cant bit of an address is not decoded If byte access is executed in the register at an odd address 2n 1 the register at the even address 2n will be accessed because of the hardware specification 2 In the V850E MS1 no registers exist which are capable of word access but if word access is executed in the register for the word area disregarding the bottom 2 bits of the address halfword access is perf...

Page 86: ...ngle chip mode 0 x0100000H to x3FFDFFFH When in single chip mode 1 x0000000H to x00FFFFFH x0200000H to x3FFDFFFH When in ROM less modes 0 and 1 x0000000H to x3FFDFFFH b µ µ µ µPD703100 703100A x0000000H to x3FFDFFFH Access to the external memory area uses the chip select signal assigned to each memory block refer to 4 4 Bus Cycle Type Control Function Note that the internal ROM internal RAM and in...

Page 87: ...ing of the MM register the external data bus width is 8 bits c In the case of single chip mode 0 At reset time since the internal ROM area is accessed each pin of ports 4 5 6 A and B enters the port mode and external devices cannot be used Set the MM register to change to the external expansion mode d In the case of single chip mode 1 Internal ROM area is allocated from address 100000H Refer to 3 ...

Page 88: ... to A11 PB5 PB7 P61 P63 P65 P67 1 0 1 0 A12 1 0 1 1 A13 A14 1 1 0 0 A15 A16 1 1 0 1 A17 A18 1 1 1 0 A19 A20 1 1 1 1 A21 A22 A23 3 to 0 MM3 to MM0 Caution Write to the MM register after reset and then do not change the set value Also do not access an external memory area other than the one for this initialization routine until the initial setting of the MM register is complete However it is possibl...

Page 89: ...and the program size can be saved To enhance the efficiency of using the pointer in connection with the memory map of the V850E MS1 the following points are recommended 1 Program space Of the 32 bits of the PC program counter the higher 6 bits are fixed to 0 and only the lower 26 bits are valid Therefore a contiguous 64 MB space starting from address 00000000H unconditionally corresponds to the me...

Page 90: ... 24 Kbytes 0001FFFFH When R r0 zero register is specified for the LD ST disp16 R instruction an addressing range of 00000000H 32 KB can be referenced with the sign extended 16 bit displacement value By mapping the external memory in the 24 KB area in the figure all resources including internal hardware can be accessed with one pointer The zero register r0 is a register set to 0 by hardware and eli...

Page 91: ...x1000000H x0FFFFFFH x0100000H x00FFFFFH x0020000H x001FFFFH x0000000H x3FFF5F7H x3FFF5F6H Data space Internal peripheral I O Internal peripheral I O Internal RAM Internal RAM External memory Internal ROM External memory External memory External memory External memory External memory Internal RAM Internal peripheral I ONote Reserved area Reserved area 64 Mbytes 16 Mbytes Internal ROM Internal ROM N...

Page 92: ...0 mode register PM0 FFFFF022H Port 1 mode register PM1 FFFFF024H Port 2 mode register PM2 FFFFF026H Port 3 mode register PM3 FFFFF028H Port 4 mode register PM4 FFFFF02AH Port 5 mode register PM5 FFFFF02CH Port 6 mode register PM6 FFFFF030H Port 8 mode register PM8 FFFFF032H Port 9 mode register PM9 FFFFF034H Port 10 mode register PM10 FFFFF036H Port 11 mode register PM11 FFFFF038H Port 12 mode reg...

Page 93: ...ator prescaler mode register 0 BPRM0 FFFFF088H Clocked serial interface mode register 0 CSIM0 00H FFFFF08AH Serial I O shift register 0 SIO0 FFFFF094H Baud rate generator compare register 1 BRGC1 Undefined FFFFF096H Baud rate generator prescaler mode register 1 BPRM1 FFFFF098H Clocked serial interface mode register 1 CSIM1 00H FFFFF09AH Serial I O shift register 1 SIO1 FFFFF0A4H Baud rate generato...

Page 94: ...rrupt control register OVIC15 FFFFF10CH Interrupt control register CMIC40 FFFFF10EH Interrupt control register CMIC41 FFFFF110H Interrupt control register P10IC0 FFFFF112H Interrupt control register P10IC1 FFFFF114H Interrupt control register P10IC2 FFFFF116H Interrupt control register P10IC3 FFFFF118H Interrupt control register P11IC0 FFFFF11AH Interrupt control register P11IC1 FFFFF11CH Interrup...

Page 95: ...rrupt control register SEIC1 FFFFF158H Interrupt control register SRIC1 FFFFF15AH Interrupt control register STIC1 FFFFF15CH Interrupt control register ADIC R W 47H FFFFF166H In service priority register ISPR R 00H FFFFF170H Command register PRCMD W Undefined FFFFF180H External interrupt mode register 0 INTM0 FFFFF182H External interrupt mode register 1 INTM1 FFFFF184H External interrupt mode regi...

Page 96: ...F1F4H DMA addressing control register 2 DADC2 FFFFF1F6H DMA addressing control register 3 DADC3 0000H FFFFF200H DRAM configuration register 0 DRC0 FFFFF202H DRAM configuration register 1 DRC1 FFFFF204H DRAM configuration register 2 DRC2 FFFFF206H DRAM configuration register 3 DRC3 3FC1H FFFFF210H Refresh control register 0 RFC0 FFFFF212H Refresh control register 1 RFC1 FFFFF214H Refresh control re...

Page 97: ...H Capture compare register 122 CC122 FFFFF298H Capture compare register 123 CC123 Undefined FFFFF2A0H Timer unit mode register 13 TUM13 0000H FFFFF2A2H Timer control register 13 TMC13 FFFFF2A4H Timer output control register 13 TOC13 R W 00H FFFFF2B0H Timer 13 TM13 R 0000H FFFFF2B2H Capture compare register 130 CC130 FFFFF2B4H Capture compare register 131 CC131 FFFFF2B6H Capture compare register 13...

Page 98: ... register 1 ADCR1 FFFFF396H A D conversion result register 1H ADCR1H FFFFF398H A D conversion result register 2 ADCR2 FFFFF39AH A D conversion result register 2H ADCR2H FFFFF39CH A D conversion result register 3 ADCR3 FFFFF39EH A D conversion result register 3H ADCR3H FFFFF3A0H A D conversion result register 4 ADCR4 FFFFF3A2H A D conversion result register 4H ADCR4H FFFFF3A4H A D conversion result...

Page 99: ...status register DDIS R FFFFF5D2H DMA restart register DRST FFFFF5E0H DMA trigger factor register 0 DTFR0 FFFFF5E2H DMA trigger factor register 1 DTFR1 FFFFF5E4H DMA trigger factor register 2 DTFR2 FFFFF5E6H DMA trigger factor register 3 DTFR3 FFFFF5F0H DMA channel control register 0 DCHC0 FFFFF5F2H DMA channel control register 1 DCHC1 FFFFF5F4H DMA channel control register 2 DCHC2 FFFFF5F6H DMA ch...

Page 100: ...ftware STOP mode insert a NOP instruction 1 instruction Example 1 MOV 0x04 r10 2 ST B r10 PRCMD r0 3 ST B r10 PSC r0 4 NOP No special sequence is required when reading the specific registers Caution Do not write to the PRCMD register or to a specific register by DMA transfer Remarks 1 A store instruction to a command register will not be received with an interrupt This presupposes that this is don...

Page 101: ...PRCMD The command register PRCMD is a register used when write accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution This register can be written in 8 bit units It becomes undefined in a read cycle Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register Address FFFFF170H 7 REG7 PRCMD 6 REG6 5...

Page 102: ... error occurred Note 0 Protection error did not occur 1 Protection error occurred 0 UNLOCK Unlock Status Flag This is an exclusive read out flag It shows that the PLL is in the unlocked state for details refer to 8 4 PLL Lockup 0 Locked 1 Unlocked Note Operation conditions of PRERR flag Set conditions PRERR 1 1 If the store instruction most recently executed to peripheral I O does not write data t...

Page 103: ...Function When in the Port Mode Register Which Performs Port Control Mode Switching Data bus D0 to D7 P40 to P47 Port 4 MM Data bus D8 to D15 P50 to P57 Port 5 MM Address bus A0 to A7 PA0 to PA7 Port A MM Address bus A8 to A15 PB0 to PB7 Port B MM Address bus A16 to A23 P60 to P67 Port 6 MM Chip select CS0 to CS7 RAS0 to RAS7 IORD IOWR P80 to P87 Port 8 PMC8 Read write control LCAS UCAS LWR UWR RD ...

Page 104: ...area Internal RAM area External memory area 3FFE000H 3E00000H 3DFFFFFH 3FFF000H 3FFEFFFH 3C00000H 3BFFFFFH 3800000H 37FFFFFH 3000000H 2FFFFFFH 1000000H 0FFFFFFH 0800000H 07FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 0 2 MB Block 1 2 MB Block 2 4 MB Block 3 8 MB Block 4 8 MB Block 5 4 MB Block 6 2 MB Block 7 2 MB Reserved area Internal ROM areaNote Note When in single chip mode 1 and ...

Page 105: ...01 0 BT00 7 6 5 4 3 2 1 0 Bit Position Bit Name Function Bus Cycle Type Specifies the external device connected to memory block n BTn1 BTn0 External Device Connected Directly to Memory Block n 0 0 SRAM external ROM external I O 0 1 Page ROM 1 0 DRAM Note 1 1 Setting prohibited 15 to 0 BTn1 BTn0 n 7 to 0 Note Using the DTC register one DRAM access type setting can be selected out of 4 types for eac...

Page 106: ...ndence with blocks 0 to 7 External Device Memory Block SRAM External ROM External I O Page ROM DRAM Block 0 Note 1 CS0 RAS0 Block 1 CS1 RAS1 Block 2 CS2 RAS2 Block 3 CS3 RAS3 Block 4 CS4 RAS4 Block 5 CS5 RAS5 Block 6 CS6 RAS6 Block 7 Note 2 CS7 RAS7 Notes 1 Except internal ROM area 2 Except internal RAM area and internal peripheral I O area ...

Page 107: ... transfer During write 3 n 3 n EDO DRAM 16 8 bits 3 n 1 n 3 n 1 n During read 3 n 2 n External device During DMA flyby transfer During write 3 n 3 n Remarks 1 Unit Clock access 2 n Number of wait insertions 1 Internal peripheral I O interface The contents of the access to internal peripheral I O are not output to the external bus Therefore during instruction fetch access internal peripheral I O ac...

Page 108: ...en in ROM less mode 0 5555H When in ROM less mode 1 0000H Bit Position Bit Name Function Data Bus Width Sets the data bus width of memory block n BSn1 BSn0 Data Bus Width of Memory Block n 0 0 8 bits 0 1 16 bits 1 Optional RFU Reserved 15 to 0 BSn1 BSn0 n 7 to 0 Cautions 1 Write to the BSC register after reset and then do not change the set value Also do not access an external memory area other th...

Page 109: ... Byte access 8 bits a When the data bus width is 16 bits 1 Access to address 2n even address 2 Access to address 2n 1 odd address 7 0 Byte data 7 0 15 8 External data bus 2n Address 7 0 Byte data 7 0 15 8 External data bus 2n 1 Address Remark n 0 1 2 3 b When the data bus width is 8 bits 1 Access to address 2n even address 2 Access to address 2n 1 odd address 7 0 Byte data 7 0 7 0 7 0 External dat...

Page 110: ...Halfword data 7 0 15 8 15 8 External data bus 2n 2 Address First Second Remark n 0 1 2 3 b When the data bus width is 8 bits 1 Access to address 2n even address 2 Access to address 2n 1 odd address 7 0 Halfword data 7 0 15 8 External data bus Address 7 0 Halfword data 7 0 15 8 External data bus 2n 2 2n 1 Address First Second 7 0 Halfword data 7 0 15 8 External data bus Address 7 0 Halfword data 7 ...

Page 111: ...4 15 8 Address 1 Access to address 4n 7 0 Word data 7 0 15 8 External data bus 4n 1 23 16 31 24 15 8 Address First 7 0 Word data 7 0 15 8 External data bus 4n 2 4n 3 23 16 31 24 15 8 Address Second 7 0 Word data 7 0 15 8 External data bus 4n 4 23 16 31 24 15 8 Address Third 2 Access to address 4n 1 7 0 Word data 7 0 15 8 External data bus 4n 3 23 16 31 24 15 8 Address First 7 0 Word data 7 0 15 8 ...

Page 112: ...data bus 4n 3 23 16 31 24 Address Third 4n 7 0 Word data 7 0 15 8 External data bus 4n 4 23 16 31 24 Address Fourth 7 0 Word data 7 0 15 8 External data bus 4n 2 23 16 31 24 4n Address First 7 0 Word data 7 0 15 8 External data bus 4n 3 23 16 31 24 Address Second 4n 7 0 Word data 7 0 15 8 External data bus 4n 4 23 16 31 24 Address Third 4n 7 0 Word data 7 0 15 8 External data bus 4n 5 23 16 31 24 ...

Page 113: ...et FFH Register Name Bit Position Bit Name Function Data Wait Specifies the number of wait states inserted in memory block n Registers DWC1 and DWC2 are set in combination DWn2 DWn1 DWn0 Number of Wait States Inserted in Memory Block n DWC1 15 to 0 DWn1 DWn0 n 7 to 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 DWC2 7 to 0 DWn2 n 7 to 0 Cautions 1 The internal ROM area and inter...

Page 114: ...e setup hold time in the sampling timing is not satisfied a wait may or may not be inserted in the next state 4 6 3 Relationship between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of programmable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is determined...

Page 115: ...DWxx 0 to 7 PRC Page ROM cycle On page Data access wait PRW0 to PRW2 0 to 7 DRCn RAS pre charge RPC0n RPC1n 0 to 3 DRCn Row address hold RHC0n RHC1n 0 to 3 DRCn Off page Data access wait DAC0n DAC1n 0 to 3 Note DRCn CAS pre charge CPC0n CPC1n 0 to 3 DRCn Read access On page Data access wait DAC0n DAC1n 0 to 3 DRCn RAS pre charge RPC0n RPC1n 0 to 3 DRCn Row address hold RHC0n RHC1n 0 to 3 Note DRCn...

Page 116: ... pre charge RPC0n RPC1n 0 to 3 DRCn Row address hold RHC0n RHC1n 0 to 3 DRCn TW DAC0n DAC1n 0 to 3 FDW Off page Data access wait TF FDWm 0 1 DRCn CAS pre charge CPC0n CPC1n 0 to 3 DRCn TW DAC0n DAC1n 0 to 3 FDW DRAM External I O On page Data access wait TF FDWm 0 1 DRCn RAS pre charge RPC0n RPC1n 0 to 3 DRCn Row address hold RHC0n RHC1n 0 to 3 DRCn TW DAC0n DAC1n 0 to 3 FDW Off page Data access wa...

Page 117: ... control register BCC This register can be read written in 16 bit units 15 BC71 BCC Address FFFFF062H After reset 5555H 14 BC70 13 BC61 12 BC60 11 BC51 10 BC50 9 BC41 8 BC40 7 BC31 6 BC30 5 BC21 4 BC20 3 BC11 2 BC10 1 BC01 0 BC00 Memory block 7 6 5 4 3 2 1 0 Bit Position Bit Name Function Bus Cycle Specifies insertion of an idle state in memory block n BCn1 BCn0 Idle State in Memory Block n 0 0 No...

Page 118: ...118 2 Idle state insertion timing T1 T2 Address Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Address T1 T2 TI Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 ...

Page 119: ...lowing timings Caution The HLDRQ function is invalid during the reset period When the RESET pin and HLDRQ pin are made active simultaneously and then the RESET pin is made inactive the HLDAK pin becomes active after a one clock idle cycle has been inserted Note that for a power on reset even if the RESET pin and HLDRQ pin are made active simultaneously and then the RESET pin is made inactive the H...

Page 120: ... HLDAK 0 6 HLDRQ 1 accepted 7 HLDAK 1 8 Clears bus cycle start request pending 9 Start of bus cycle 4 8 3 Operation in power save mode In the STOP or IDLE mode the internal system clock is stopped Consequently the bus hold state is not accepted and set even if the HLDRQ pin becomes active In the HALT mode the HLDAK pin immediately becomes active when the HLDRQ pin becomes active and the bus hold s...

Page 121: ...IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST HLDRQ HLDAK A0 to A23 CLKOUT Data TH TH TH TI TI Note If HLDRQ signal is inactive high level at this sampling timing bus hold state is not entered Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 4 Timing from DRAM access to bus hold state ...

Page 122: ...s CPU 4 10 Boundary Operation Conditions 4 10 1 Program space 1 Branching to the peripheral I O area or successive fetch from the internal RAM area to the internal peripheral I O area is prohibited In terms of hardware fetching the NOP op code continues and fetching from the external memory is not performed 2 If a branch instruction exists at the upper limit of the internal RAM area a pre fetch op...

Page 123: ...o boundary alignment the bus cycle will be generated at least 2 times and bus efficiency will drop 1 In the case of halfword length data access When the address s lowest bit is a 1 the byte length bus cycle will be generated 2 times 2 In the case of word length data access a When the address s lowest bit is a 1 bus cycles will be generated in the order of byte length bus cycle halfword length bus ...

Page 124: ...User s Manual U12688EJ4V0UM00 124 MEMO ...

Page 125: ...rface 5 1 1 SRAM connections An example of connection to SRAM is shown below Figure 5 1 Example of Connection to SRAM A0 to A16 I O1 to I O8 1 Mbit 128 K 8 SRAM CS WE OE VCC A1 to A17 D0 to D7 D8 to D15 CSn UWR LWR V850E MS1 RD 5 V 5 V 5 V HVDD A0 to A16 I O1 to I O8 1 Mbit 128 K 8 SRAM CS WE OE VCC Remark n 0 to 7 ...

Page 126: ...O access Figure 5 2 SRAM External ROM External I O Access Timing 1 4 a During read T1 T2 Address Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Address TW T2 T1 Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 ...

Page 127: ...M External ROM External I O Access Timing 2 4 b During write T1 T2 Address Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Address TW T2 T1 Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 ...

Page 128: ...Timing 3 4 c During DMA flyby transfer SRAM External I O T1 T2 Address Data Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Address Address T2 TF T1 TW T2 T1 DMAAKm Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 4 m 0 to 3 ...

Page 129: ...Timing 4 4 d During DMA flyby transfer External I O SRAM T1 T2 Address Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Data Address Address T2 TF T1 TW T2 T1 DMAAKm Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 4 m 0 to 3 ...

Page 130: ...e widths of from 8 to 64 bytes 5 2 1 Features It can connect directly to 8 bit 16 bit page ROM When the bus width is 16 bits it can handle 4 8 16 32 word page access When the bus width is 8 bits it can handle 8 16 32 64 word page access Individual wait settings 0 to 7 waits for off page and on page are possible 5 2 2 Page ROM connections Examples of page ROM connections are shown below Figure 5 3 ...

Page 131: ...0 131 Figure 5 3 Example of Page ROM Connections 2 2 b In the case of 16 Mbit 2 M 8 page ROM 16 Mbit page ROM 2 M 8 A0 to A19 O0 to O7 WORD BYTE OE CE 16 Mbit page ROM 2 M 8 A0 to A19 O0 to O7 WORD BYTE OE CE A1 to A20 D8 to D15 D0 to D7 RD CSn V850E MS1 Remark n 0 to 7 ...

Page 132: ... address no comparison is made according to the configuration of the connected page ROM and the number of continuously readable bits Figure 5 4 On Page Off Page Judgment for Page ROM Connection 1 2 a In the case of 16 Mbit 1 M 16 page ROM 4 word page access a23 a22 a21 a20 a19 a18 a5 a4 a3 A23 A22 A21 A20 A19 A18 A5 A4 A3 A2 A1 A0 A19 Internal address latch V850E MS1 address output Page ROM addres...

Page 133: ...Internal address latch V850E MS1 address output Page ROM address A18 A17 Off page address On page address Continuous reading possible 16 bit data bus width 8 words A4 A3 A2 A1 A0 MA5 0 MA4 0 MA3 1 PRC register setting Comparison a23 a22 a21 a20 a19 a18 a5 a4 a3 A23 A22 A21 A20 A19 A18 A5 A4 A3 A2 A1 A0 A 1 A19 Internal address latch V850E MS1 address output Page ROM address A18 A17 Off page addres...

Page 134: ...nal system clock The waits set by this bit are inserted only for on page access For off page access the waits set by registers DWC1 and DWC2 are inserted refer to 4 6 Wait Function PRW2 PRW1 PRW0 Number of Inserted Wait Cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 6 to 4 PRW2 to PRW0 Mask Address Each address A5 to A3 corresponding to MA5 to MA3 is masked by 1 The masked ...

Page 135: ...Figure 5 5 Page ROM Access Timing T1 TW Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Off page address On page address On page address TO1 TO2 T2 Remarks 1 The circle indicates the sampling timing 2 The broken lines indicate high impedance 3 n 0 to 7 ...

Page 136: ...age DRAM and EDO DRAM Supports the RAS hold mode 4 types of DRAM can be assigned to 8 memory block spaces Can handle 2CAS type DRAM Can be switched between row and column address multiplex widths Waits 0 to 3 waits can be inserted at the following timings Row address precharge wait Row address hold wait Data access wait Column address precharge wait Supports CBR refresh and CBR self refresh ...

Page 137: ...A9 I O1 to I O16 RAS LCAS 16 Mbit 1 M 16 DRAM UCAS OE WE A1 to A10 D0 to D15 RASn LCAS UCAS V850E MS1 WE OE b In the case of 4 Mbit 1 M 4 DRAM A1 to A10 D0 to D7 D8 to D15 RASn LCAS UCAS V850E MS1 WE OE A0 to A9 I O1 to I O4 RAS CAS 4 Mbit 1 M 4 DRAM WE OE A0 to A9 I O1 to I O4 RAS CAS 4 Mbit 1 M 4 DRAM WE OE A0 to A9 I O1 to I O4 RAS CAS 4 Mbit 1 M 4 DRAM WE OE A0 to A9 I O1 to I O4 RAS CAS 4 Mbi...

Page 138: ...igure 5 7 Row Address Column Address Output Row address DAW1n DAW0n 11 Address pin A23 to A18 a23 to a18 A17 a17 A16 a16 A15 a15 A14 a25 A13 a24 A12 a23 A11 a22 A10 a21 A9 a20 A8 a19 A7 a18 A6 a17 A5 a16 A4 a15 A3 a14 A2 a13 A1 a12 A0 a11 Row address DAW1n DAW0n 10 a23 to a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 Row address DAW1n DAW0n 01 a23 to a18 a17 a25 a24 a...

Page 139: ... DAC 01 DAC 11 RHC 01 RHC 11 RPC 01 RPC 11 PAE 01 PAE 11 0 0 0 DAW 02 DAW 12 CPC 02 CPC 12 DAC 02 DAC 12 RHC 02 RHC 12 RPC 02 RPC 12 PAE 02 PAE 12 0 0 0 DAW 03 DAW 13 CPC 03 RHD 0 RHD 1 RHD 2 RHD 3 CPC 13 DAC 03 DAC 13 RHC 03 RHC 13 RPC 03 RPC 13 PAE 03 PAE 13 0 0 0 14 15 DRC0 FFFFF202H 3FC1H DRC1 FFFFF204H 3FC1H DRC2 FFFFF206H 3FC1H DRC3 Bit Position Bit Name Function DRAM On page Access Mode Con...

Page 140: ... Specifies the number of wait states inserted as column address precharge time CPC1n CPC0n Number of Wait States Inserted 0 0 0 Note 0 1 1 1 0 2 1 1 3 7 6 CPC1n CPC0n Note 1 wait is inserted during DRAM write access in DMA flyby transfer 4 RHDn RAS Hold Disable Sets the RAS hold mode If access to DRAM during on page operation is not continuous and access enters another space midway the RASm signal...

Page 141: ...W0n Address Multiplex Width 0 0 8 bits 0 1 9 bits 1 0 10 bits 1 1 11 bits 1 0 DAW1n DAW0n Caution Write to the DRCn register after reset and then do not change the set value Also do not access an external memory area other than the one for this initialization routine until the initial setting of the DRCn register is complete However it is possible to access an external memory area whose initializa...

Page 142: ...tion Bit Name Function DRAM Type Configuration Specifies the DRAM configuration register n DRCn corresponding to memory block m Furthermore it has no meaning if the memory block m is not specified in the DRAM area DCm1 DCm0 DRAM Configuration Register n DRCn Corresponding to Memory Block m 0 0 DRC0 0 1 DRC1 1 0 DRC2 1 1 DRC3 15 to 0 DCm1 DCm0 Caution Write to the DTC register after reset and then ...

Page 143: ... Read timing 1 T1 T2 Column address Row address Column address Column address WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data TO1 TO2 TO1 TO2 T3 Data Data Remarks 1 This is the timing in the case of no waits 2 The circle indicates the sampling timing 3 The broken lines indicate high impedance 4 n 0 to 7 ...

Page 144: ...TCPW TO1 TDAW TO2 TCPW TO1 TDAW TO2 TRHW Data Data Column address Column address Column address Row address Remarks 1 This is the timing in the following cases 00 to 03 10 to 13 Number of waits according to bit RPC TRPW 1 Number of waits according to bit RHC TRHW 1 Number of waits according to bit DAC TDAW 1 Number of waits according to bit CPC TCPW 1 2 The circle indicates the sampling timing 3 T...

Page 145: ...ming 1 T1 T2 Column address Row address Column address Column address WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Data Data TO1 TO2 TO1 TO2 T3 Data Remarks 1 This is the timing in the case of no waits 2 The circle indicates the sampling timing 3 The broken lines indicate high impedance 4 n 0 to 7 ...

Page 146: ... TCPW TO1 TDAW TO2 TCPW TO1 TDAW TO2 TRHW Data Data Column address Column address Column address Row address Remarks 1 This is the timing in the following cases 00 to 03 10 to 13 Number of waits according to bit RPC TRPW 1 Number of waits according to bit RHC TRHW 1 Number of waits according to bit DAC TDAW 1 Number of waits according to bit CPC TCPW 1 2 The circle indicates the sampling timing 3 ...

Page 147: ... T1 T2 WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Column address TB TE TB Data Data Data Optional Column address Column address Row address Remarks 1 This is the timing in the case of no waits 2 The circle indicates the sampling timing 3 The broken lines indicate high impedance 4 n 0 to 7 ...

Page 148: ...KOUT Data Data Column address Column address Column address T2 TDAW TCPW TB TCPW TE TB TDAW TDAW TRHW Remarks 1 This is the timing in the following cases 00 to 03 10 to 13 Number of waits according to bit RPC TRPW 1 Number of waits according to bit RHC TRHW 1 Number of waits according to bit DAC TDAW 1 Number of waits according to bit CPC TCPW 1 2 The circle indicates the sampling timing 3 The bro...

Page 149: ...g 3 4 c Write timing 1 T1 T2 WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT Column address TB TE TB Data Data Data Optional Column address Column address Row address Remarks 1 This is the timing in the case of no waits 2 The broken lines indicate high impedance 3 n 0 to 7 ...

Page 150: ...ASn BCYST A0 to A23 CLKOUT Data Data Column address Column address Column address T2 TDAW TCPW TB TCPW TE TB TDAW TDAW TRHW Remarks 1 This is the timing in the following cases 00 to 03 10 to 13 Number of waits according to bit RPC TRPW 1 Number of waits according to bit RHC TRHW 1 Number of waits according to bit DAC TDAW 1 Number of waits according to bit CPC TCPW 1 2 The broken lines indicate hi...

Page 151: ... T2 Column address Row address Data WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST A0 to A23 CLKOUT TF TO1 TO2 TF TO1 TO2 TF T3 DMAAKm Column address Data Data Column address Remarks 1 This is the timing in the case where wait TF insertion setting was carried out according to the FDW register 2 The circle indicates the sampling timing 3 The broken lines indicate high impedance ...

Page 152: ... address TCPWNote TO1 TO2 TCPW TO1 TO2 T3 DMAAKm Column address Data Data Note A minimum of 1 clock cycle is inserted for the TCPW cycle regardless of the CPC0m and CPC1m bit settings in the DRCm register Remarks 1 This is the timing in the case where the number of waits according to the CPC bit TCPW is 1 00 to 03 10 to 13 2 In the case of external I O DRAM the FDW register setting is invalid 3 Th...

Page 153: ...ation formula Refresh interval µs Refresh count clock TRCY Interval factor The refresh count clock and interval factor are determined by the RENn bit and RIn bit respectively of the RFCn register Note that n corresponds to the register number 0 to 3 of DRAM configuration registers 0 to 3 DRC0 to DRC3 These registers can be read written in 16 bit units 0 RI 00 Address FFFFF210H After reset 0000H 1 ...

Page 154: ...9 8 RCCn1 RCCn0 Refresh Interval Sets the interval factor of the interval timer for generation of refresh timing RIn5 RIn4 RIn3 RIn2 RIn1 RIn0 Interval Factor 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 1 1 1 1 1 1 64 5 to 0 RIn5 to RIn0 Caution After refresh enable if changing the refresh count clock or the interval factor first clear the RENn bit 0 refresh disable state then perform ...

Page 155: ...Refresh Interval Value µs Refresh Count Clock TRCY When φ 16 MHz When φ 20 MHz When φ 33 MHz When φ 40 MHz 32 φ 7 14 9 14 4 15 14 5 19 15 2 128 φ 1 8 2 12 8 3 11 6 4 12 8 15 6 256 φ 1 12 8 1 7 8 2 12 8 32 φ 30 60 38 60 8 63 61 1 128 φ 7 56 9 57 6 15 58 2 19 60 8 62 5 256 φ 3 48 4 51 2 7 54 3 9 57 6 32 φ 128 φ 15 120 19 121 6 32 124 1 39 124 8 125 256 φ 7 112 9 115 2 16 124 1 19 121 6 32 φ 128 φ 31...

Page 156: ... number of wait states inserted as hold time for the RASm signal s low level width during CBR refresh RCW2 RCW1 RCW0 Number of Insertion Wait States 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 5 to 3 RCW2 to RCW0 Self refresh Release Wait Control Specifies the number of wait states inserted as CBR self refresh release time SRW2 SRW1 SRW0 Number of Insertion Wait States 0 0 0 0 ...

Page 157: ... IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST REFRQ A0 to A23 CLKOUT TRCWNote TRCW T3 TI T2 Optional Note A minimum of 1 clock cycle is inserted for the TRCW cycle regardless of the RCW0 to RCW2 bit settings in the RWC register Remarks 1 This is the timing in the case where the number of waits TRCW according to the bits RCW0 to RCW2 is 1 2 n 0 to 7 ...

Page 158: ... a self refresh operation mode n 0 to 7 To release the self refresh cycle follow either of two methods below 1 Release by NMI input a In the case of self refresh cycle with IDLE mode Set the RASn LCAS UCAS signals to inactive high level immediately to release the self refresh cycle b In the case of self refresh cycle with software STOP mode Set the RASn LCAS UCAS signals to inactive high level aft...

Page 159: ... IDLE Mode TRRW TH TH TH TH TH TH TRCW TH TI WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST REFRQ A0 to A23 CLKOUT TSRW TSRW NMI Remarks 1 This is the timing in the following cases Number of waits according to bits RRW0 and RRW1 TRRW 1 Number of waits according to bits RCW0 to RCW2 TRCW 1 Number of waits according to bits SRW0 to SRW2 TSRW 2 2 n 0 to 7 ...

Page 160: ...tware STOP Mode TRRW TH TH TH TH TH TH TRCW TH TI WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS WE OE RD CSn RASn BCYST REFRQ A0 to A23 CLKOUT TSRW TSRW NMI Remarks 1 This is the timing in the following cases Number of waits according to bits RRW0 and RRW1 TRRW 1 Number of waits according to bits RCW0 to RCW2 TRCW 1 Number of waits according to bits SRW0 to SRW2 TSRW 2 2 n 0 to 7 ...

Page 161: ...ulse unit DMARQ0 to DMARQ3 pins or software triggers 6 1 Features 4 independent DMA channels Transfer unit 8 16 bits Maximum transfer count 65 536 216 Two types of transfer Flyby one cycle transfer Two cycle transfer Three transfer modes Single transfer mode Single step transfer mode Block transfer mode Transfer requests DMARQ0 to DMARQ3 pin 4 Requests from internal peripheral I O serial interface...

Page 162: ...C V850E MS1 Bus interface External bus External RAM External ROM External I O DMA source address register DSAnH DSAnL DMA byte count register DBCn DMA addressing control register DADCn DMA channel control register DCHCn DMA destination address register DDAnH DDAnL NMI DMARQn DMAAKn INTPmn Internal peripheral I O request DMA disable status register DDIS DMA restart register DRST DMA trigger factor ...

Page 163: ... n DDAn is ignored 1 DMA source address registers 0H to 3H DSA0H to DSA3H These registers can be read written in 16 bit units Bit Position Bit Name Function 9 to 0 SA25 to SA16 Source Address Sets the DMA source address A25 to A16 During DMA transfer it stores the next DMA source address During flyby transfer between external memory and external I O it stores a memory address 0 SA 16 Address FFFFF...

Page 164: ...een external memory and external I O it stores a memory address 0 SA 0 Address FFFFF1A2H After reset Undefined 1 SA 1 2 SA 2 3 SA 3 4 SA 4 5 SA 5 6 SA 6 7 SA 7 8 SA 8 9 SA 9 10 11 12 13 14 15 DSA0L FFFFF1AAH Undefined DSA1L FFFFF1B2H Undefined DSA2L FFFFF1BAH Undefined SA 10 SA 11 SA 12 SA 13 SA 14 SA 15 SA 0 SA 1 SA 2 SA 3 SA 4 SA 5 SA 6 SA 7 SA 8 SA 9 SA 10 SA 11 SA 12 SA 13 SA 14 SA 15 SA 0 SA ...

Page 165: ...ion address registers 0H to 3H DDA0H to DDA3H These registers can be read written in 16 bit units 0 DA 16 Address FFFFF1A4H After reset Undefined 1 DA 17 2 DA 18 3 DA 19 4 DA 20 5 DA 21 6 DA 22 7 DA 23 8 DA 24 9 DA 25 10 0 11 0 12 0 13 0 14 0 15 0 DDA0H DA 16 FFFFF1ACH Undefined DA 17 DA 18 DA 19 DA 20 DA 21 DA 22 DA 23 DA 24 DA 25 0 0 0 0 0 0 DDA1H DA 16 FFFFF1B4H Undefined DA 17 DA 18 DA 19 DA 2...

Page 166: ... DA 0 DA 1 DA 2 DA 3 DA 4 DA 5 DA 6 DA 7 DA 8 DA 9 DA 10 DA 11 DA 12 DA 13 DA 14 DA 15 DA 0 DA 1 DA 2 DA 3 DA 4 DA 5 DA 6 DA 7 DA 8 DA 9 DA 10 DA 11 DA 12 DA 13 DA 14 DA 15 DA 0 DA 1 DA 2 DA 3 DA 4 DA 5 DA 6 DA 7 DA 8 DA 9 DA 10 DA 11 DA 12 DA 13 DA 14 DA 15 DDA3L Bit Position Bit Name Function 15 to 0 DA15 to DA0 Destination Address Sets the DMA destination address A15 to A0 During DMA transfer i...

Page 167: ...C 4 5 BC 5 6 BC 6 7 BC 7 8 BC 8 9 BC 9 10 11 12 13 14 15 DBC0 FFFFF1E2H Undefined DBC1 FFFFF1E4H Undefined DBC2 FFFFF1E6H Undefined BC 10 BC 11 BC 12 BC 13 BC 14 BC 15 BC 0 BC 1 BC 2 BC 3 BC 4 BC 5 BC 6 BC 7 BC 8 BC 9 BC 10 BC 11 BC 12 BC 13 BC 14 BC 15 BC 0 BC 1 BC 2 BC 3 BC 4 BC 5 BC 6 BC 7 BC 8 BC 9 BC 10 BC 11 BC 12 BC 13 BC 14 BC 15 BC 0 BC 1 BC 2 BC 3 BC 4 BC 5 BC 6 BC 7 BC 8 BC 9 BC 10 BC 1...

Page 168: ... SAD 0 7 SAD 1 8 DS 9 10 0 11 0 12 0 13 0 14 0 15 0 DADC0 FFFFF1F2H 0000H TTYP TM 0 TM 1 DAD 0 DAD 1 SAD 0 SAD 1 DS 0 0 0 0 0 0 DADC1 FFFFF1F4H 0000H TTYP TM 0 TM 1 DAD 0 DAD 1 SAD 0 SAD 1 DS 0 0 0 0 0 0 DADC2 FFFFF1F6H 0000H TTYP TDIR TDIR TDIR TDIR TM 0 TM 1 DAD 0 DAD 1 SAD 0 SAD 1 DS 0 0 0 0 0 0 0 0 0 0 DADC3 Bit Position Bit Name Function 8 DS Data Size Sets the transfer data size for DMA tran...

Page 169: ... Transfer Mode Sets the transfer mode during DMA transfer TM1 TM0 Transfer Mode 0 0 Single transfer mode 0 1 Single step transfer mode 1 0 Block transfer mode 1 1 Setting prohibited 3 2 TM1 TM0 1 TTYP Transfer Type Sets the DMA transfer type 0 Two cycle transfer 1 Flyby transfer 0 TDIR Transfer Direction Sets the transfer direction during transfer between I O and memory The setting is valid during...

Page 170: ...DCHC3 Bit Position Bit Name Function 7 TCn Terminal Count This status bit indicates whether DMA transfer through DMA channel n has ended or not This bit can only be read It is set 1 when DMA transfer ends with a terminal count and reset 0 when it is read 0 DMA transfer has not ended 1 DMA transfer has ended 2 INITn Initialize If this bit is set 1 the DMA transfer is forcibly terminated 1 STGn Soft...

Page 171: ...C32 IFC33 IFC34 IFC35 0 0 DTFR0 FFFFF5E2H 00H DTFR1 FFFFF5E4H 00H DTFR2 FFFFF5E6H 00H DTFR3 Bit Position Bit Name Function Interrupt Factor Code This code indicates the source of the DMA transfer trigger IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source 0 0 0 0 0 0 DMA request from internal peripheral I O disabled 0 0 0 0 0 1 INTCM40 0 0 0 0 1 0 INTCM41 0 0 0 0 1 1 INTCSI0 0 0 0 1 0 0 INTSR0 0 ...

Page 172: ... 0 1 0 INTP133 INTCC133 0 1 1 0 1 1 INTP140 INTCC140 0 1 1 1 0 0 INTP141 INTCC141 0 1 1 1 0 1 INTP142 INTCC142 0 1 1 1 1 0 INTP143 INTCC143 0 1 1 1 1 1 INTP150 INTCC150 1 0 0 0 0 0 INTP151 INTCC151 1 0 0 0 0 1 INTP152 INTCC151 1 0 0 0 1 0 intp153 intcc153 1 0 0 0 1 1 INTAD Other than above Setting prohibited 5 to 0 IFCn5 to IFCn0 Remark n 0 to 3 Remark The relationship between the DMARQn signal an...

Page 173: ...at was forcibly interrupted during NMI input The RENn bit of this register and the ENn bit of the DCHCn register are linked to each other n 0 to 3 After NMI is completed the DDIS register is referred to and the DMA channel that was interrupted is confirmed then by setting the RENn bit in the corresponding channel 1 DMA transfer can be restarted The register can be read written in 8 or 1 bit units ...

Page 174: ...W1 2 FDW2 3 FDW3 4 FDW4 5 FDW5 6 FDW6 7 FDW7 0 1 2 3 4 5 6 7 FDW Memory Block Bit Position Bit Name Function 7 to 0 FDWn n 7 to 0 Flyby Data Wait Sets wait state insertion for memory block n 0 Wait state not inserted 1 Wait state inserted Caution Write to the FDW register after reset and then do not change the value Also do not access an external memory area until the initial setting of the FDW re...

Page 175: ...n the last T2R state read data is sampled After entering the last T2R state the bus invariably enters the T1W state 6 T2RI state Internal peripheral I O or internal RAM DMA transfer ready state Bus mastership is acquired for DMA transfer to internal peripheral I O or internal RAM After entering the last T2RI state the bus invariably enters the T1W state 7 T1W state The bus enters the T1W state at ...

Page 176: ... continued or not If the next transfer is executed in block transfer mode the bus enters the T1FRB state after the T3FR state otherwise the bus enters the T4 state 16 T1FRB state The bus enters the T1FRB state at the beginning of a flyby block transfer from internal RAM to internal peripheral I O The read cycle from internal RAM is started 17 T1FRBI state The T1FRBI state corresponds to a wait sta...

Page 177: ... T2FH is a state in which it is judged whether a flyby transfer between external memory and external I O is continued or not If the next transfer is executed in block transfer mode the bus enters the T1FH state after the T2FH state otherwise when a wait is issued the bus enters the T1FHI state When a wait is not issued the bus is released and enters the TE state 24 T3 state The bus enters the T3 s...

Page 178: ... each time the processing for a DMA service is completed the bus is released the bus enters bus release mode Figure 6 1 DMAC Bus Cycle State Transition Diagram a Two cycle transfer b Flyby transfer TI T0 T1R T1RI T2R T1W T2W T3 TE TI T2RI T1WI TI T0 T1F T1FH T2F T3F T3 TE TI T2FH T1FHI T1FR T2FR T3FR T1FRB T1FRBI T2FRB T3FRB T4 ...

Page 179: ... and 6 3 show examples of single transfer Figure 6 3 shows an example of single transfer in which a higher priority DMA request is issued DMA channels 0 to 2 are in block transfer mode and channel 3 is in single transfer mode Figure 6 2 Single Transfer Example 1 CPU DMARQ3 CPU DMA3 CPU DMA3 CPU DMA3 CPU CPU CPU CPU CPU CPU DMA3 CPU DMA3 CPU CPU CPU DMA channel 3 terminal count Figure 6 3 Single Tr...

Page 180: ...PU CPU CPU DMA1 CPU DMA1 CPU DMA0 CPU DMA0 CPU DMA0 CPU DMA1 CPU DMA1 CPU DMA channel 0 terminal count DMA channel 1 terminal count DMARQ1 DMARQ0 6 5 3 Block transfer mode In block transfer mode once transfer starts the transfer continues without the bus being released until a terminal count occurs No other DMA requests are accepted during block transfer After the block transfer ends and DMAC rele...

Page 181: ...fer Note that caution is required when in two cycle transfer For details refer to 6 19 Precautions Figure 6 7 Timing of Two Cycle Transfer 1 4 a Block transfer mode SRAM DRAM TI TI TI TI WAIT IOWR IORD LWR LCAS UWR UCAS OE RD BCYST DRAM area CSj RASj A0 to A23 D0 to D15 CLKOUT DMARQn DMAAKn TCn Internal DMA request signal BCU states DMAC states T1 T1R T1 T1W T2 T2R T1 T1R TO1 T1W TO2 T2W TW T2R T2...

Page 182: ... T1R TW T2R T2 T2R T1 T1W TW T2W T2 T2W TE TI Address Data Data Data Data Address Address Address BCU states DMAC states CLKOUT DMARQn Internal DMA request signal DMAAKn TCn A0 to A23 D0 to D15 External I O area CSj RASj SRAM area CSk RASk BCYST RD OE WE UWR UCAS LWR LCAS IORD IOWR WAIT Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 3 j 0 to 7 k ...

Page 183: ...O DRAM TI DMAC states TI D0 to D15 TCn Internal DMA request signal A0 to A23 CLKOUT TI T0 T0 T1R T2R T2R TI T1 T1W CPU states T3 T2W T3 T3 TE TI T2 T2W CSm RASm OE RD WE IOWR IORD DMAAKn DMARQn LWR LCAS UWR UCAS BCYST Row address Column address Data WAIT Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 3 m 0 to 7 ...

Page 184: ...l I O TI DMAC states TI D0 to D15 TCn Internal DMA request signal A0 to A23 CLKOUT TI T0 TI T1W CPU states T2W T3 T3 TE TI T2W T2RI T1 T1R T3 T2R T2 T2R CSm RASm OE RD WE IOWR IORD DMAAKn DMARQn LWR LCAS UWR UCAS BCYST Row address Column address Data WAIT Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 3 m 0 to 7 ...

Page 185: ...the read write strobe signals for the memory and I O are made active at the same time The external I O is selected with the DMAAK0 to DMAAK3 signal Figure 6 8 shows examples of flyby DMA transfer for an external device Figure 6 8 Timing of Flyby Transfer DRAM External I O 1 3 a Block transfer mode TI TI WAIT D0 to D15 IOWR IORD LWR LCAS UWR UCAS RD CSm RASm BCYST A0 to A23 CLKOUT TI T0 T1 T1FH T2 ...

Page 186: ... T3 T1FHI TI T0 TE TI TI TI TE T1 T1FH T2 T1FHI T3 T1FHI TI TI Data Data Columnaddress CPU states DMAC states CLKOUT DMARQn Internal DMA request signal DMAAKn TCn A0 to A23 D0 to D15 CSm RASm BCYST RD OE WE UWR UCAS LWR LCAS IORD IOWR WAIT Row address Row address Columnaddress Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 3 m 0 to 7 ...

Page 187: ...D LWR LCAS UWR UCAS OE RD BCYST A0 to A23 D0 to D15 CSm RASm CLKOUT DMARQn DMAAKn TCn Internal DMA request signal CPU states DMAC states T1 T1FH T3 T1FHI T2 T1FHI T0 T3 T1FHI T1 T1FH T2 T1FHI TE TI T0 TI TE TI WE Data Data Column address Row address Column address Row address Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 3 m 0 to 7 ...

Page 188: ...MA transfer block transfer mode between internal RAM and internal peripheral I O Figure 6 9 Timing of Flyby Transfer Internal Peripheral I O Internal RAM TI TI TI TI Internal peripheral I O address bus Internal address bus Internal data bus CLKOUT DMARQn DMAAKn TCn H Internal DMA request signal T2F T2F T3 T3 T3F T3F T3F T1F T0 T0 T1F TE TI Data Data Data Data Address Address Address Address Remark...

Page 189: ...during DMA transfer is as follows Table 6 2 External Bus Cycle During DMA Transfer Transfer Type Transfer Object External Bus Cycle Internal peripheral I O Internal RAM None Note External I O Yes SRAM cycle Two cycle transfer External memory Yes Memory access cycle set in the BCT register Between internal RAM and internal peripheral I O None Note Flyby transfer Between external memory and external...

Page 190: ...ting Function The DMA source address registers DSAnH DSAnL DMA destination address registers DDAnH DDAnL and DMA byte count register DBCn are buffer registers with a 2 stage FIFO configuration n 0 to 3 When the terminal count is issued these registers are rewritten with the value that was set just previously Therefore during DMA transfer these registers contents do not become valid even if they ar...

Page 191: ...DCHCn register 1 and the TCn bit 0 is set the DMARQn signal in the T1 state becomes active If the DMARQn signal becomes active in the T1 state it changes to the T0 state and DMA transfer starts 2 Request from software If the STGn ENn and TCn bits of the DCHCn register are set as follows DMA transfer starts n 0 to 3 STGn bit 1 ENn bit 1 TCn bit 0 3 Request from internal peripheral I O If when the E...

Page 192: ...fer being executed when the NMI was input is terminated n 0 to 3 When in the single step mode or block transfer mode the DMA transfer request is held in the DMAC If the ENn bit is reset 1 DMA transfer restarts from the point where it was interrupted When in the single transfer mode if the ENn bit is set 1 the next DMA transfer request is received and DMA transfer starts 6 12 Terminating DMA Transf...

Page 193: ...ion DMA channel 3 transfer start DMA channel 2 transfer is forcibly terminated The bus is released DMARQ3 CPU CPU CPU CPU DMA2 DMA2 DMA2 DMA2 DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU b During block transfer through DMA channel 1 transfer is terminated and a different conditional transfer is executed DSA1 DDA1 DBC1 DADC1 DCHC1 DCHC1 INIT1 bit 1 Register set DSA1 DDA1 DBC1 Register set Register set ...

Page 194: ...MA transfer and minimum execution clock for DMA transfer Table 6 3 Minimum Execution Clock in DMA Cycle From accepting DMARQn to falling edge of DMAAKn 4 clocks External memory access Refer to miscellaneous memory and I O cycle Internal RAM access 2 clocks Internal peripheral I O access 3 clocks From rising edge of DMAAKn to falling edge of TCn 1 clock Remark n 0 to 3 6 16 Maximum Response Time to...

Page 195: ...dition 3 Condition Instruction fetch from external memory at the 8 bit data bus width Execution of the bit manipulation instruction SET1 CLR1 NOT1 Response time Tinst 4 Tdata 2 Tref DMARQn input DMAAKn output D0 to D15 input output Fetch 1 4 Data read Fetch 2 4 Fetch 3 4 Fetch 4 4 Data write Refresh DMA cycle Remarks 1 Tinst The number of clocks per bus cycle during instruction fetch Tdata The num...

Page 196: ... Table 6 4 DMAAKn Active DMARQn Inactive Time for Single Transfer to External Memory Transfer Type Source Destination DMAAKn Signal Active DMARQn Inactive Time Max Note DRAM off page All objects 5 clocks DRAM on page All objects 4 clocks SRAM or external I O All objects 4 clocks Internal RAM or internal peripheral I O DRAM off page 7 clocks Internal RAM or internal peripheral I O DRAM on page 6 cl...

Page 197: ... While data transfer is being executed between internal RAM and internal peripheral I O the CPU can access external memory and external I O 6 19 Precaution If a DMA transfer which satisfies all the following conditions is interrupted by NMI input the DMAAKn signal may become active and remain so until the next DMA transfer n 0 to 3 Two cycle transfer Block transfer mode Transfer from external memo...

Page 198: ...User s Manual U12688EJ4V0UM00 198 MEMO ...

Page 199: ...and external sources Moreover exception processing can be started by the TRAP instruction software exception or by the generation of an exception event fetching of an illegal op code which is known as an exception trap 7 1 Features Interrupts Non maskable interrupts 1 source Maskable interrupts 47 sources 8 levels of programmable priorities Mask specification for interrupt requests according to pr...

Page 200: ...100 pin CC100 Pin RPU 6 0100H 00000100H nextPC Interrupt INTP101 INTCC101 P10IC1 Match of INTP101 pin CC101 Pin RPU 7 0110H 00000110H nextPC Interrupt INTP102 INTCC102 P10IC2 Match of INTP102 pin CC102 Pin RPU 8 0120H 00000120H nextPC Interrupt INTP103 INTCC103 P10IC3 Match of INTP103 pin CC103 Pin RPU 9 0130H 00000130H nextPC Interrupt INTP110 INTCC110 P11IC0 Match of INTP110 pin CC110 Pin RPU 10...

Page 201: ...C Interrupt INTP151 INTCC151 P15IC1 Match of INTP151 pin CC151 Pin RPU 27 0250H 00000250H nextPC Interrupt INTP152 INTCC152 P15IC2 Match of INTP152 pin CC152 Pin RPU 28 0260H 00000260H nextPC Interrupt INTP153 INTCC153 P15IC3 Match of INTP153 pin CC153 Pin RPU 29 0270H 00000270H nextPC Interrupt INTCM40 CMIC40 CM40 match signal RPU 30 0280H 00000280H nextPC Interrupt INTCM41 CMIC41 CM41 match sign...

Page 202: ...IO 45 03C0H 000003C0H nextPC Maskable Interrupt INTAD ADIC A D conversion completion ADC 46 0400H 00000400H nextPC Caution INTP1mn external interrupt and INTCC1mn compare register match interrupt share a control register m 0 to 5 n 0 to 3 Set the valid interrupt request using bits 3 to 0 IMS1mn of timer unit mode registers 10 to 15 TUM10 to TUM15 see 9 3 1 Timer unit mode registers 10 to 15 TUM10 ...

Page 203: ...r 3 2 1 0 3210 3210 Selector 3 2 1 0 3210 3210 Selector xxPRn0 to xxPRn3 Interrupt priority order specification bit 3 2 1 0 INTOV10 INTOV11 INTOV12 INTOV13 INTOV14 INTOV15 INTCM40 INTCM41 INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTCSI0 INTSER0 INTSR0 INTST0 INTCSI1 INTSER1 INTSR1 INTST1 INTCSI2 INTCSI3 INTAD INTP100 INTCC100 INTP101 INTCC101 INTP102 INTCC102 INTP103 INTCC103 INTP110 INTCC110 INTP111 INTCC...

Page 204: ...gister 0 INTM0 is detected on the NMI pin the interrupt occurs While the service program of the non maskable interrupt is being executed PSW NP 1 the acknowledgement of another non maskable interrupt requests is held pending The pending NMI is acknowledged after the original service program of the non maskable interrupt under execution has been terminated by the RETI instruction or when PSW NP is ...

Page 205: ...halfword FECC of ECR 4 Sets the NP and ID bits of PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The processing configuration of a non maskable interrupt is shown in Figure 7 2 Figure 7 2 Processing Configuration of Non Maskable Interrupt PSW NP FEPC FEPSW ECR FECC PSW NP PSW EP PSW ID PC restored PC PSW 00...

Page 206: ...quest NMI request PSW NP 1 NMI request held pending because PSW NP 1 Pending NMI request processed b If a new NMI request is generated twice while an NMI service program is being executed Main routine NMI request NMI request Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two or more NMI requests are generated NMI request Held pending be...

Page 207: ...2 Transfers control back to the address of the restored PC and PSW Figure 7 4 illustrates how the RETI instruction is processed Figure 7 4 RETI Instruction Processing PSW EP RETI instruction PSW NP Original processing restored 1 1 0 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt processing in order ...

Page 208: ...sing 1 NMI interrupt currently being processed 7 2 4 Noise elimination NMI pin noise is eliminated with analog delay The delay time is 60 to 220 ns The signal input that changes within the delay time is not internally acknowledged The NMI pin is used for releasing the software STOP mode In the software STOP mode the internal system clock is not used for noise elimination because the internal syste...

Page 209: ...her priority than the interrupt requests in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiplexed interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose register before executing the EI ...

Page 210: ...terrupt currently being processed Priority higher than that of other interrupt request Highest default priority of interrupt requests with the same priority EIPC EIPSW ECR EICC PSW EP PSW ID PC restored PC PSW exception code 0 1 handler address The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is being processed when PSW NP 1 or PSW ID 1 are he...

Page 211: ...ers control to the address of the restored PC and PSW Figure 7 6 illustrates the processing of the RETI instruction Figure 7 6 RETI Instruction Processing PSW EP RETI instruction PSW NP Restores original processing 1 1 0 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during maskable interrupt processing in order to restore t...

Page 212: ...pt control register xxICn When two or more interrupts having the same priority level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 7 1 The programmable priority control customizes interrupt requests into eight le...

Page 213: ...n that of a and interrupts are enabled Although the priority of interrupt request d is higher than that of c d is held pending because interrupts are disabled Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g Interrupt reques...

Page 214: ... 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k which occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because processing of l is performed in the interrupt disabled status Pending ...

Page 215: ...routine EI Interrupt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Processing of interrupt request b Processing of interrupt request c Processing of interrupt request a Interrupt requests b and c are acknowledged first according to their priorities Because the priorities of b and c are the same b is acknowledged first because it has the higher default priority ...

Page 216: ...ask flag 0 Enables interrupt processing 1 Disables interrupt processing pending Priority 8 levels of priority order are specified in each interrupt xxPRn2 xxPRn1 xxPRn0 Interrupt Priority Specification Bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Specifies level 4 1 0 1 Specifies level 5 1 1 0 Specifies level 6 1 1 1 Specifies le...

Page 217: ... P13IF1 P13MK1 0 0 0 P13PR12 P13PR11 P13PR10 FFFFF12CH P13IC2 P13IF2 P13MK2 0 0 0 P13PR22 P13PR21 P13PR20 FFFFF12EH P13IC3 P13IF3 P13MK3 0 0 0 P13PR32 P13PR31 P13PR30 FFFFF130H P14IC0 P14IF0 P14MK0 0 0 0 P14PR02 P14PR01 P14PR00 FFFFF132H P14IC1 P14IF1 P14MK1 0 0 0 P14PR12 P14PR11 P14PR10 FFFFF134H P14IC2 P14IF2 P14MK2 0 0 0 P14PR22 P14PR21 P14PR20 FFFFF136H P14IC3 P14IF3 P14MK3 0 0 0 P14PR32 P14PR...

Page 218: ...priority n not acknowledged 1 Interrupt request with priority n acknowledged Remark n 0 to 7 priority level 7 3 6 Maskable interrupt status flag ID The ID flag is bit 5 of the PSW This controls the maskable interrupt s operating state and stores control information on enabling disabling acknowledgement of interrupt requests 31 0 PSW After reset 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 ...

Page 219: ...3 INTP130 to INTP133 INTP140 to INTP143 INTP150 to INTP152 INTP153 ADTRG φ 2 φ to 3 φ Remark φ Internal system clock Figure 7 9 Example of Noise Elimination Timing Sampling clock fSMP Input signal Internal signal Rising edge detection Falling edge detection Max 3 clocksNote 1 Min 2 clocksNote 2 Notes 1 Pulse width of unrecognizable noise 2 Pulse width of recognizable signals Cautions 1 If the inpu...

Page 220: ...pling clock Valid edges are specified in external interrupt mode registers 1 to 6 INTM1 to INTM6 1 External interrupt mode registers 1 to 6 INTM1 to INTM6 These are registers that specify the valid edge for external interrupt requests INTP100 to INTP103 INTP110 to INTP113 INTP120 to INTP123 INTP130 to INTP133 INTP140 to INTP143 INTP150 to INTP152 INTP153 ADTRG by external pins The correspondence b...

Page 221: ... ES101 ES100 ES231 ES230 ES221 ES220 ES211 ES210 ES201 ES200 INTP103 INTP102 INTP101 INTP100 Control pins INTP113 INTP112 INTP111 INTP110 Control pins INTP123 INTP122 INTP121 INTP120 Control pins INTP133 INTP132 INTP131 INTP130 Control pins FFFFF18AH INTM5 00H FFFFF18CH INTM6 00H ES531 ES530 ES521 ES520 ES511 ES510 ES501 ES500 ES431 ES430 ES421 ES420 ES411 ES410 ES401 ES400 INTP143 INTP142 INTP141...

Page 222: ...errupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 7 10 illustrates how a software exception is processed Figure 7 10 Software Exception Processing TRAP instruction EIPC EIPSW ECR EICC PSW EP PSW ID PC restored PC PSW exception code 1 1 handler address CPU processing Exc...

Page 223: ... the address of the restored PC and PSW Figure 7 11 illustrates the processing of the RETI instruction Figure 7 11 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception process in order to restore the PC and P...

Page 224: ...t exception processing is in progress It is set when an exception occurs 31 0 PSW After reset 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Position Bit Name Function 6 EP Exception Pending Shows that exception processing is in progress 0 Exception processing not in progress 1 Exception processing in progress ...

Page 225: ...ted in the case where the sub op code of the following instruction is an illegal op code when execution of that instruction is attempted 7 5 1 Illegal op code definition The illegal op code has a 32 bit long instruction format bits 10 to 5 are 111111B and bits 26 to 23 are 0111B to 1111B with bit 16 defined as an optional instruction code 0B 15 16 17 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 ...

Page 226: ...o DBPC 3 Sets the NP EP and ID bits of PSW 4 Sets the handler address 00000060H corresponding to the exception trap to the PC and transfers control Figure 7 12 illustrates how the exception trap is processed Figure 7 12 Exception Trap Processing 7 5 3 Restore Recovery from an exception trap is not possible Perform system reset by RESET input Exception trap ILGOP occurs DBPC DBPSW PSW NP PSW EP PSW...

Page 227: ...ing control is executed when an interrupt has an enable status ID 0 Thus if multiple interrupts are executed it is necessary to have an interrupt enable status ID 0 even for an interrupt processing routine If a maskable interrupt or a software exception is generated in a maskable interrupt or software exception service program it is necessary to save EIPC and EIPSW This is accomplished by the foll...

Page 228: ... request register xxlCn which is provided for each maskable interrupt request At system reset time an interrupt request is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits The priority order of maskable interrupts is as follows High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt processing that has been suspended as a resu...

Page 229: ...instruction fetch ID Invalid instruction decode Interrupt Latency Time Internal System Clock Internal interrupt External interrupt Condition Minimum 5 7 Maximum 11 13 The following cases are exceptions In IDLE software STOP mode External bus is accessed Two or more interrupt request non sample instructions are executed in succession Access to interrupt control register 7 8 Periods in Which Interru...

Page 230: ...User s Manual U12688EJ4V0UM00 230 MEMO ...

Page 231: ...ing a PLL phase locked loop synthesizer Clock Source Oscillation by connecting an oscillator fXX φ 5 External clock fXX 2 φ φ 5 Power save control HALT mode IDLE mode Software STOP mode Clock output inhibit function Internal system clock output function 8 2 Configuration X1 X2 Clock generator CG φ CKSEL fXX CPU Internal peripheral I O Time base counter TBC CLKOUT Remark φ Internal system clock fre...

Page 232: ... can be saved Mainly the V850E MS1 is used in application systems where it operates at relatively low frequencies In consideration of EMI countermeasures if the external clock frequency fXX is 32 MHz internal system clock φ 16 MHz or greater the PLL mode is recommended Caution In the direct mode be sure to input an external clock do not connect an external resonator 8 3 2 PLL mode In the PLL mode ...

Page 233: ... After reset 00H Bit Position Bit Name Function Clock Divide Sets the internal system clock frequency φ when in the PLL mode CKDIV1 CKDIV0 Internal System Clock φ 0 0 5 fXX 0 1 Setting prohibited 1 0 fXX 1 1 fXX 2 1 0 CKDIV1 CKDIV0 The sequence of setting data to this register is the same as for the power save control register PSC However the restrictions shown in Remark 2 of 3 4 9 Specific regist...

Page 234: ... is kept at 0 and is not initialized when system reset occurs 0 Indicates that the PLL is in a locked state 1 Indicates that the PLL is not locked in an unlocked state Remark For an explanation of the PRERR flag refer to 3 4 9 2 System status register SYS If the clock stops the power fails or some other factor occurs to cause the unlocked state in control processing which depends on software execu...

Page 235: ...ware STOP mode and the HALT mode in relation to clock stabilization time and current consumption and is used for cases where the low current consumption mode is used and where it is desired to eliminate the clock stabilization time after it is released 3 Software STOP mode In this mode the clock generator oscillator and PLL synthesizer is stopped and the system overall is stopped thus entering an ...

Page 236: ...lation by resonator Software STOP mode During normal operation HALT mode IDLE mode PLL mode Software STOP mode During normal operation HALT mode IDLE mode Direct mode External clock Software STOP mode Operating Stopped Figure 8 1 Power Save Mode State Transition Diagram Normal operating mode Software STOP mode Software STOP mode setting IDLE mode IDLE mode setting Released by RESET NMI input HALT ...

Page 237: ...Select Selects the time base counter clock 0 fXX 2 8 1 fXX 2 9 Details are shown in 8 6 2 Time base counter TBC 4 CESEL Crystal External Select Specifies the function of pins X1 and X2 0 An oscillator is connected to pins X1 and X2 1 An external clock is connected to pin X1 If CESEL 1 the oscillator s feedback loop is cut and current leakage is prevented when in the software STOP mode Also the osc...

Page 238: ...an the ports that is not dependent on CPU instruction processing continues operation The state of each hardware unit when in the HALT mode is shown in Table 8 2 Remark Even after HALT instruction execution instruction fetch operations continue until the internal instruction prefetch queue becomes full When the prefetch queue becomes full it stops in the state shown in Table 8 2 Table 8 2 Operating...

Page 239: ...rrupt request under execution is generated the HALT mode is released but the newly generated interrupt request is not acknowledged The new interrupt request will be kept pending ii If an interrupt request with a priority higher including NMI request than the interrupt request under execution is generated the HALT mode is released and the interrupt request is also acknowledged Table 8 3 Operations ...

Page 240: ...c registers In the IDLE mode program execution is stopped but all the contents of all the registers internal RAM and ports are held Operation of the internal peripheral I O except the ports is also stopped The state of each hardware unit when in IDLE mode is as shown in Table 8 4 Table 8 4 Operating States When in IDLE Mode Function Operating State Clock generator Operating Internal system clock S...

Page 241: ...ending The interrupt processing that is started when the IDLE mode is released by NMI pin input is treated in the same way as ordinary NMI interrupt processing in an emergency etc since the NMI interrupt handler s address is unique Consequently in cases where it is necessary to distinguish between the two in a program it is necessary to prepare the software status in advance and set the status bef...

Page 242: ...are STOP mode Operation of the internal peripheral I O except the ports is also stopped The status of each hardware unit during the software STOP mode is as shown in Table 8 5 Caution In the case of the direct mode CKSEL pin 1 or external clock connection mode CESEL bit of the PSC register 1 the software STOP mode cannot be used Table 8 5 Operating States When in Software STOP Mode Function Operat...

Page 243: ...y to distinguish between the two it is necessary to prepare the software status in advance and set the status before setting the PSC register using the store instruction or a bit operation instruction By checking this status in NMI interrupt processing it is possible to distinguish it from an ordinary NMI b Release by RESET Pin Input This is the same as an ordinary reset operation 8 5 6 Clock outp...

Page 244: ...input active edge detection TBC count time After the proper time start internal system clock output and branch to the NMI interrupt handler address Oscillation waveform Software STOP mode setting Oscillator stopped Internal system clock CLKOUT output STOP state NMI input Time base counter current time The NMI pin should normally be set at the inactive level for example so that it changes to high l...

Page 245: ...time is secured until the clock output from the oscillator stabilizes After inputting the rising edge to the RESET pin supply of the internal system clock begins and the system branches to the handler address that was set at system reset time Oscillation waveform Software STOP mode setting Oscillator stopped Internal system clock STOP state Internal system reset signal Oscillation stabilization ti...

Page 246: ...s counted by the TBC and after counting is ended program execution begins The TBC count clock is selected by the TBCS bit in the PSC register and it is possible to set the following count times refer to 8 5 2 1 Power save control register PSC Table 8 6 Example of Count Time φ φ φ φ 5 fXX Count Time fXX 3 2768 MHz fXX 5 0000 MHz fXX 6 5536 MHz fXX 8 0000 MHz TBCS Bit Count Clock φ 16 384 MHz φ 25 0...

Page 247: ... be generated interval pulse one shot pulse Timer 1 16 bit timer event counter Count clock sources 2 types internal system clock division selection external pulse input Capture compare common registers 24 Count clear pins TCLR10 to TCLR15 Interrupt sources 30 types External pulse outputs 12 Timer 4 16 bit interval timer The count clock is selected from the internal system clock divisions Compare r...

Page 248: ...rigger TM12 Read INTOV12 External clear CC120 Read write INTCC120 INTP120 TO120 S CC121 Read write INTCC121 INTP121 TO120 R CC122 Read write INTCC122 INTP122 TO121 S CC123 Read write INTCC123 INTP123 TO121 R TM13 Read INTOV13 External clear CC130 Read write INTCC130 INTP130 TO130 S CC131 Read write INTCC131 INTP131 TO130 R CC132 Read write INTCC132 INTP132 TO131 S CC133 Read write INTCC133 INTP133...

Page 249: ...INTP153 INTCC153 TCLR10 TI10 INTP100 INTP101 INTP102 INTP103 TCLR11 TI11 INTP110 INTP111 INTP112 INTP113 TM11 Selector Selector Selector Selector S Q Q R IMS100 IMS101 IMS102 IMS103 TM15 TCLR15 TI15 INTP150 INTP151 INTP152 INTP153 Selector Selector Selector Selector Selector S CC100 TM10 16 bit TM10 ETI10 1 4 1 2 1 8 1 16 m Note 2 Note3 Note3 Note 1 PRS100 PRS101 PRM 101 Edge detection Edge detect...

Page 250: ...E PULSE UNIT User s Manual U12688EJ4V0UM00 250 2 Timer 4 16 bit interval timer 1 2 1 16 Internal count clock 1 32 PRM400 PRM401 PRS400 TM40 16 bit CM40 TM41 TM40 Clear start INTCM40 INTCM41 1 4 1 8 Selector Selector Internal system clock m φ φ ...

Page 251: ...erformed by the TMC1n register a Selection of an external count clock TM1n operates as an event counter The active edge is specified by the timer unit mode register 1n TUM1n and through input of pin TI1n TM1n is counted up b Selection of an internal count clock TM1n operates as a free running timer The counter clock can be selected from among the divisions performed by the prescaler φ 2 φ 4 φ 8 φ ...

Page 252: ...gister in response to an instruction are in contention the latter has the priority and the capture operation is disregarded Also specification of the active edge of external interrupts rising falling or both edges can be selected by the external interrupt mode register INTM1 to INTM6 When there is a specification in the capture register an interrupt is issued when the active edge of INTP1n0 to INT...

Page 253: ...scaler via register TMC4n Caution Since the timer is cleared at the next count clock after a compare match is issued when the division ratio is large even if the timer s value is read immediately after the match interrupt is issued the timer s value may not be 0 Also the count clock cannot be changed during timer operation 2 Compare registers 40 41 CM40 CM41 CM4n is a 16 bit register and is connec...

Page 254: ...ES 130 CES 131 CES 130 CMS 133 CMS 132 CMS 131 CMS 130 IMS 133 IMS 132 IMS 131 IMS 130 0 TUM14 FFFFF2C0H 0000H 0 OST4 ECLR 14 TES 141 TES 140 CES 141 CES 140 CMS 143 CMS 142 CMS 141 CMS 140 IMS 143 IMS 142 IMS 141 IMS 140 0 TUM15 FFFFF2E0H 0000H 0 OST5 ECLR 15 TES 151 TES 150 CES 151 CES 150 CMS 153 CMS 152 CMS 151 CMS 150 IMS 153 IMS 152 IMS 151 IMS 150 Bit Position Bit Name Function 13 OSTn Over...

Page 255: ...dge 1 0 RFU reserved 1 1 Both the rising and falling edges 9 8 CES1n1 CES1n0 7 to 4 CMS1nm m 3 to 0 Capture Compare Mode Select Selects the capture compare register s CC1nm operation mode 0 Operates as a capture register However the capture operation when it is specified as a capture register is performed only when the CE1n bit of the TMC1n register 1 1 Operates as a compare register 3 to 0 IMS1nm...

Page 256: ...e external trigger input becomes the A D converter starting trigger starting the conversion operation When this happens the external trigger input also functions as Timer 1 s capture trigger and as an external interrupt In order for it not to issue capture triggers or external interrupts set Timer 1 in the compare register and disable interrupts with the interrupt control register s interrupt mask...

Page 257: ...E15 TMC15 0 0 ETI15 PRS151 PRS150 PRM151 0 00H Bit Position Bit Name Function 7 CE1n Count Enable Controls timer operation 0 The timer is stopped in the 0000H state and does not operate 1 The timer performs a count operation However when the ECLR1n bit of the TUM1n register is 1 the timer does not start counting up until there is a TCLR1n input When the ECLR1n bit is 0 the operation of setting 1 i...

Page 258: ...t Selects the internal count clock φm is the intermediate clock PRS1n1 PRS1n0 Internal Count Clock 0 0 φm 0 1 φm 4 1 0 φm 8 1 1 φm 16 3 2 PRS1n1 PRS1n0 1 PRM1n1 Prescaler Clock Mode Selects the intermediate count clock φm φ is the internal system clock 0 φ 2 1 φ 4 Caution Do not change the count clock during timer operation Remark n 0 to 5 ...

Page 259: ...41 0 0 0 0 PRS410 PRM411 PRM410 00H Bit Position Bit Name Function 7 CE4n Count Enable Controls timer operations 0 The timer is stopped in the 0000H state and does not operate 1 The timer performs a count operation 2 PRS4n0 Prescaler Clock Select Selects the internal count clock φm is the intermediate clock 0 φm 16 1 φm 32 Prescaler Clock Mode Selects the intermediate count clock φm φ is the inter...

Page 260: ...isabled The reverse phase level inactive level of the ALV1n0 and ALV1n1 bits is output from the TO1n0 and TO1n1 pins Even if a match signal is generated by the corresponding compare register the level of the TO1n0 and TO1n1 pins does not change 1 Timer output is enabled If a match signal is generated from the corresponding compare register the timer s output changes From the timer that timer outpu...

Page 261: ...41 TOVS 6 OVF40 5 OVF15 4 OVF14 3 OVF13 2 OVF12 1 OVF11 0 OVF10 After reset 00H Bit Position Bit Name Function 7 to 0 OVF41 OVF40 OVF15 to OVF10 Overflow Flag This is the overflow flag for TM41 TM40 and TM1n 0 No overflow is generated 1 Overflow is generated Caution Interrupt requests INTOV1n for the interrupt controller are generated in synch with an overflow from TM1n but because interrupt opera...

Page 262: ...he CC1n0 to CC1n3 registers an interrupt signal is generated and timer output signal TO1n0 and TO1n1 can be set reset In addition a capture operation that holds the current count value of TM1n and loads it into one of the four registers CC1n0 to CC1n3 is performed in synchronization with the valid edge detected from the corresponding external interrupt request pin as an external trigger The captur...

Page 263: ...lock rates φ 2 φ 4 φ 8 φ 16 φ 32 or φ 64 by the setting of the PRS1n1 PRS1n0 and PRM1n1 bits of the TMC1n register PRS1n1 PRS1n0 PRM1n1 Internal Count Clock 0 0 0 φ 2 0 0 1 φ 4 0 1 0 φ 8 0 1 1 φ 16 1 0 0 φ 16 1 0 1 φ 32 1 1 0 φ 32 1 1 1 φ 64 Remark n 0 to 5 2 External count clock ETI1n bit 1 This counts the signals input to the TI1n pin At this time Timer 1 can be operated as an event counter The ...

Page 264: ...ated n 0 to 5 Also by setting the OSTn bit 1 in the TUM1n register the timer can be stopped after overflow If the timer is stopped due to an overflow the count operation does not resume until the CE1n bit in the TMC1n register is set 1 Note that even if the CE1n bit is set 1 during a count operation it has no influence on operation Figure 9 2 Operation after Overflow If ECLR1n 0 and OSTn 1 Overflo...

Page 265: ...ed and the count operation resumes refer to Figure 9 3 If the ECLR1n bit of the TUM1n register is set to 1 and the OSTn bit is set to 1 the counting operation starts if the active edge is input to the TCLR1n signal after the CE1n bit is set 1 If TM1n overflows the count operation stops once and it does not resume the count operation until the active edge is input again to the TCLR1n signal If the ...

Page 266: ...external interrupt request input pins INTP1n0 to INTP1n3 is used as the external trigger capture trigger In synch with that capture trigger signal the count value of TM1n as it is counting is captured and held in the capture register The value in the capture register is held until the next capture trigger is generated Also interrupt requests INTCC1n0 to INTCC1n3 are generated from the INTP1n0 to I...

Page 267: ...ing and falling edges are made capture triggers the input pulse width from an external source can be measured Also if the edge from one side is used as the capture trigger the input pulse s period can be measured Figure 9 5 Example of Capture Operation TM11 0 CE11 INTP110 CC110 n n Capture trigger Capture trigger Remark When the CE11 bit 0 no capture operation is performed even if INTP110 is input...

Page 268: ... Manual U12688EJ4V0UM00 268 Figure 9 6 Example of TM11 Capture Operation When Both Edges Are Specified FFFFH TM11 count value CE11 1 count start OVF11 1 overflow D0 D1 D2 D0 D1 D2 Interrupt request INTP110 Capture register CC110 Remark D0 to D2 TM11 count value ...

Page 269: ...put pins TO1n0 TO1n1 are changed by the match signal and simultaneously issue interrupt request signals Table 9 3 Interrupt Request Signals TM1n from 16 Bit Compare Registers Compare Register Interrupt Request Signal CC1n0 INTCC1n0 CC1n1 INTCC1n1 CC1n2 INTCC1n2 CC1n3 INTCC1n3 Remarks 1 CC1n0 to CC1n3 are capture compare registers Which register will be used is specified by the timer unit mode regi...

Page 270: ...way the TM1n count value and the CC1n2 value are compared and if they match the TO1n1 pin s output level is set Also the TM1n counter value and the CC1n3 value are compared and if they match the TO1n1 pin s output level is set The output level of pins TO1n0 and TO1n1 can also be specified by the TOC1n register Figure 9 8 Example of TM11 Compare Operation Set Reset Output Mode TM11 count value 0 FF...

Page 271: ... Figure 9 9 Basic Operation of Timer 4 0001H 0000H 0002H 0003H FBFEH FBFFH 0001H 0002H 0000H 0003H TM4n Count clock Count disable CE4n 0 Count start CE4n 1 Count start CE4n 1 Remark n 0 1 9 5 2 Count clock selection Using the setting of the TMC4n register s PRS4n0 PRM4n1 and PRM4n0 bits one of four possible internal count clocks φ 32 φ 64 φ 128 or φ 256 can be selected n 0 1 Caution Do not change ...

Page 272: ...0 with the following timing refer to Figure 9 10 a Through this function Timer 4 is used as an interval timer CM4n can also be set to 0 In this case if TM4n overflows and becomes 0 a value match is detected and INTCM4n is issued Using the following count timing the TM4n value is cleared 0 but with this match INTCM4n is not issued refer to Figure 9 10 b Figure 9 10 Example of TM40 Compare Operation...

Page 273: ...UNIT User s Manual U12688EJ4V0UM00 273 Figure 9 10 Example of TM40 Compare Operation 2 2 b If 0 is set in CM40 1 0 0 0 FFFFH Overflow TM40 Count clock CM40 TM40 clear Match detected INTCM40 Count up Clear Remark Interval time FFFFH 1 count clock cycle ...

Page 274: ...n 0 1 Figure 9 11 Example of Timing in Interval Timer Operation n TM40 count value 0 Interrupt request INTCM40 Compare register CM40 n Count start Clear Clear n t Remark n Value in the CM40 register t Interval time n 1 count clock cycle Figure 9 12 Example of Interval Timer Operation Setting Procedure Interval timer initial setting TMC4n register setting Specifies the count clock Setting the count...

Page 275: ...is fetched to and held in the capture compare register CC112 The pulse width is calculated by determining the difference between the count value of TM11 captured in the CC112 register through active edge detection the nth time and the count value Dn 1 captured through active edge detection the n 1 th time then multiplying this value by the count clock Figure 9 13 Example of Pulse Measurement Timin...

Page 276: ...ng the TUM11 register TUM11 CMS112 0 Specifies both edges of the INTP112 input signal as active edges Sets it as the capture register Sets the CE11 bit 1 INTP112 interrupt Figure 9 15 Example of Interrupt Request Processing Routine Which Calculates the Pulse Width INTP112 interrupt processing both the rising and falling edges Calculating the pulse width Yn CC112 Xn 1 tn Yn count clock period Xn Yn...

Page 277: ... used as a 16 bit timer the PWM output s rise timing set in the capture compare register CC100 is determined as shown in Figure 9 16 and the fall timing is determined by the value set in the capture compare register CC101 Figure 9 16 Example of PWM Output Timing FFFFH FFFFH FFFFH CC100 D00 D10 D01 D11 D02 CC101 CC101 CC100 CC100 TM10 count value 0 Matching Matching Matching Matching Matching Captu...

Page 278: ...e CC100 register CC100 D00 Setting of the count value in the CC101 register CC101 D10 Count start TMC10 CE10 1 Enabling interrupt Specifies the operation of the CC100 and CC101 registers specifies compare operation Specifies the TM10 s count clock Sets the CE10 bit 1 INTCC100 interrupt INTCC101 interrupt Figure 9 18 Example of Interrupt Request Processing Routine for Rewriting Compare Value INTCC1...

Page 279: ... the INTP110 input signal is specified to be the rising edge by the INTM2 register The frequency is calculated by determining the difference between the TM11 count value Dn captured in the CC110 register from the nth rising edge and the count value Dn 1 captured from the rising edge the n 1 th time then multiplying this value by the count clock Figure 9 19 Example of Frequency Measurement Timing F...

Page 280: ...ng buffer memory for capture data storage X0 0 Count start TMC11 CE11 1 Enabling interrupt Specifies the count clock Specifies operation of the CC110 register as the capture register Specifies the rising edge of the INTP110 signal as the active edge Sets the CE11 bit 1 Figure 9 21 Example of Interrupt Request Processing Routine Which Calculates the Frequency Calculating the period Yn 10000H Xn 1 C...

Page 281: ...llowing cases a match does not occur 1 When rewriting the compare register TM10 to TM15 TM40 TM41 n Ð 1 n n 1 m n Writing to the register L Match does not occur Match does not occur Count clock Timer value Compare register value Match detection 2 During external clear TM10 to TM15 n 1 L Match does not occur External clear input 0 0000H n Ð 1 Count clock Timer value Compare register value Match det...

Page 282: ... TM40 TM41 FFFEH FFFFH 0 Internal matching clear 0 1 Count clock Timer value Match detection Match does not occur 0000H Compare register value Remark When operating timer 1 as the free running timer the timer s value becomes 0 when timer overflow occurs FFFEH FFFFH 1 Overflow interrupt 0 3 2 Count clock Timer value ...

Page 283: ...l interface UART0 UART1 2 channels 2 Clocked serial interface CSI0 to CSI3 4 channels UART0 and UART1 use the method of transmitting and receiving 1 byte of serial data following the start bit and full duplex communication is possible CSI0 to CSI3 carry out data transfer with 3 types of signal lines a serial clock SCK0 to SCK3 serial input SI0 to SI3 and serial output SO0 to SO3 3 wire serial I O ...

Page 284: ... 2 pin configuration TXDn Transmit data output pin RXDn Receive data input pin Receive error detection functions Parity error Framing error Overrun error Interrupt sources 3 types Receive error interrupt INTSERn Reception complete interrupt INTSRn Transmission complete interrupt INTSTn The character length of transmit receive data is specified by the ASIMn0 and ASIMn1 registers Character length 7 ...

Page 285: ...but left set 1 The transmit status flag is set 1 when transmission starts and is cleared 0 when transmission ends 3 Receive control parity check Receive operations are controlled according to the contents set in the ASIMn0 and ASIMn1 registers Also errors such as parity errors are checked during receive operations If an error is detected a value corresponding to the error content is set in the ASI...

Page 286: ...pecify TXS0L and TXS1L 7 Adding transmit control parity In accordance with the contents set in the ASIMn0 and ASIMn1 registers start bits parity bits stop bits etc are added to the data written to the TXSn or TXSnL register and transmit operation control is carried out 8 Selector This selects the serial clock source Figure 10 1 Block Diagram of Asynchronous Serial Interface UART1 UART0 RXD1 RXD0 R...

Page 287: ...elected 0 1 Reception enabled 1 0 Transmission enabled 1 1 Transmission reception enabled 7 6 TXEn RXEn When reception is disabled the receive shift register does not detect the start bit The receive buffer contents are held without shift in processing or transmit processing to the receive buffer being performed While in the reception enabled state the receive shift operation is started in synchro...

Page 288: ... of bits in the receive data and parity bit which are 1 is counted and if it is an odd number a parity error is generated Odd parity This is the opposite of even parity with the number of bits in the transmit data and parity bit being controlled so that it is an odd number During receiving if the number of bits in the receive data and parity bit which are 1 turns out to be an even number a parity ...

Page 289: ...ote Internal System Clock φ 16 01 8 10 4 11 40 MHz 1 250 K 2 500 K 33 MHz 1 031 K 2 062 K 4 125 K 25 MHz 781 K 1 562 K 3 125 K 20 MHz 625 K 1 250 K 2 500 K 16 MHz 500 K 1 000 K 2 000 K 12 5 MHz 390 K 781 K 1 562 K 10 MHz 312 K 625 K 1 250 K 8 MHz 250 K 500 K 1 000 K 5 MHz 156 K 312 K 625 K 1 0 SCLSn1 SCLSn0 Note Values in are the set values for the SCLSn1 and SCLSn0 bits If SCLSn1 SCLSn0 00 The ba...

Page 290: ...led 1 Expansion bit operation enabled When expansion bit is specified 1 data bit is added to the high order of 8 bit transmit receive data and communications by 9 bit data are enabled Expansion bit operation is enabled only in the case where no parity operations have been specified in the ASIMn0 register If 0 parity or even odd parity operation is specified the EBSn bit specification is made inval...

Page 291: ...1 Transmission start timing writing to the TXSn or TXSnL register Clear 0 Transmission end timing generation of the INTSTn interrupt When about to start serial data transmission use this as a means of judging whether writing to the transmit shift register is enabled or not 2 PEn Parity Error This is a status flag that shows a parity error Set 1 When transmit parity and receive parity do not match ...

Page 292: ...mpleted and the contents of the receive buffer are held Also a reception complete interrupt request is not generated RXB0 and RXB1 are read only registers in 16 bit units and RXB0L and RXB1L are read only registers in 8 or 1 bit units 15 0 RXB0 Address FFFFF0C8H After reset Undefined 14 0 13 0 12 0 11 0 10 0 9 0 8 RXEB0 7 RXB07 6 RXB06 5 RXB05 4 RXB04 3 RXB03 2 RXB02 1 RXB01 0 RXB00 RXB0L FFFFF0CA...

Page 293: ...0CCH After reset Undefined 14 0 13 0 12 0 11 0 10 0 9 0 8 TXED0 7 TXS07 6 TXS06 5 TXS05 4 TXS04 3 TXS03 2 TXS02 1 TXS01 0 TXS00 TXS0L FFFFF0CEH Undefined 7 TXS07 6 TXS06 5 TXS05 4 TXS04 3 TXS03 2 TXS02 1 TXS01 0 TXS00 15 0 TXS1 FFFFF0DCH Undefined 14 0 13 0 12 0 11 0 10 0 9 0 8 TXED1 7 TXS17 6 TXS16 5 TXS15 4 TXS14 3 TXS13 2 TXS12 1 TXS11 0 TXS10 TXS1L FFFFF0DEH Undefined 7 TXS17 6 TXS16 5 TXS15 4...

Page 294: ...eive errors In the reception disabled state no receive error interrupt is generated 2 Reception completion interrupt INTSRn In the reception enabled state a reception complete interrupt is generated when data is shifted into the receive shift register and transferred to the receive buffer This reception complete interrupt request is also generated when a receive error has occurred but the receive ...

Page 295: ...its INTSRn interrupt INTSTn interrupt Start bit 1 bit Character bits 7 bits 8 bits Parity expansion bit Even parity odd parity 0 parity no parity expansion bit Stop bit 1 bit 2 bits Remark n 0 1 2 Transmission Transmission starts when data is written to the transmit shift register TXSn or TXSnL With the transmission complete interrupt INTSTn processing routine the next data is written to the TXSn ...

Page 296: ...Sn or TXSnL register the transmit operation is interrupted After 1 transmission is ended the transmission rate drops if the next transmit data is not written to the TXSn or TSXnL register immediately Cautions 1 Normally when the transmit shift register TXSn or TXSnL has become empty a transmission complete interrupt INTSTn is generated However when RESET is input if the transmit shift register TXS...

Page 297: ...after 8 serial clock cycles If it is low this is recognized as a start bit the receive operation is started and the RXDn pin input is subsequently sampled at intervals of 16 serial clock cycles If the RXDn pin input is found to be high when sampled again 8 serial clock cycles after an RXDn pin low level is detected this low level is not recognized as a start bit the operation is stopped by initial...

Page 298: ...ASISn register in the receive error interrupt INTSERn which error occurred during reception can be detected As for the contents of the ASISn register either the receive buffer RXBn or RXBnL are read or it is reset 0 by reception of the next data if there is an error in the next receive data that error flag is set Receiving Error Cause Parity error The parity specification during transmission does ...

Page 299: ...3 10 3 2 Configuration CSIn are controlled by the clocked serial interface mode registers CSIMn Transmission reception data can be read from and written to the SIOn registers n 0 to 3 1 Clocked serial interface mode registers CSIM0 to CSIM3 The CSIMn registers are 8 bit registers that specify CSIn operations 2 Serial I O shift registers SIO0 to SIO3 The SIOn registers are 8 bit registers that conv...

Page 300: ...t controls whether or not an interrupt request is generated when the serial clock counter counts 8 clocks Figure 10 6 Block Diagram of Clocked Serial Interface SO0 CTXE0 CRXE0 CSI0 CLS00 CLS01 SO Latch 1 2 1 4 BRG0 INTCSI0 1 2 1 4 BRG1 INTCSI1 D Q Serial I O shift register SIO0 Serial clock controller Serial clock counter Interrupt controller SI0 SCK0 Selector SO1 SI1 SCK1 1 2 1 4 INTCSI2 SO2 SI2 ...

Page 301: ...ate 1 Transmission enabled state When CTXEn 0 the impedance of both the SOn and SIn pins becomes high 6 CRXEn CSI Receive Enable Specifies the receive enabled disabled state 0 Reception disabled state 1 Reception enabled state When transmission is enabled CTXEn 1 and reception is disabled if a serial clock is being input 0 is input to the shift register If reception is disabled CRXEn 0 while recei...

Page 302: ...ated Baud Rate Generators 0 to 2 BRG0 to BRG2 concerning setting of the BPRMm registers m 0 to 2 2 φ 4 and φ 2 are divider signals φ Internal system clock Cautions 1 When setting the CLSn1 and CLSn0 bits do so in the transmission reception disabled CTXEn bit CRXEn bit 0 state If the CLSn1 and CLSn0 bits are set in a state other than transmission reception disabled subsequent operation may not be n...

Page 303: ...can be read written in 8 or 1 bit units Address FFFFF08AH 7 SIO07 SIO0 6 SIO06 5 SIO05 4 SIO04 3 SIO03 2 SIO02 1 SIO01 0 SIO00 After reset Undefined FFFFF09AH SIO17 SIO1 SIO16 SIO15 SIO14 SIO13 SIO12 SIO11 SIO10 Undefined FFFFF0AAH SIO27 SIO2 SIO26 SIO25 SIO24 SIO23 SIO22 SIO21 SIO20 Undefined FFFFF0BAH SIO37 SIO3 SIO36 SIO35 SIO34 SIO33 SIO32 SIO31 SIO30 Undefined Bit Position Bit Name Function 7...

Page 304: ...rising edge of SCKn SCKn stops when the serial clock counter overflows at the rising edge of the 8th count and SCKn remains high until the next data transmission or reception is started At the same time a transmission reception complete interrupt INTCSIn is generated Caution Even if CTXEn bit is changed from 0 to 1 after the transmit data is written to the SIOnL registers serial transfer will not ...

Page 305: ...mes high impedance or UARTn output TXDn CSI2 CSI3 The serial output becomes high impedance If the CTXEn bit 1 the shift register data is output 2 If the CRXEn bit 0 the shift register input becomes 0 If the CRXEn bit 1 the serial input is input to the shift register 3 In order to receive transmit data itself and check if a bus conflict is occurring set CTXEn bit CRXEn bit 1 3 Starting transmit rec...

Page 306: ...tarted the serial clock is output from the SCKn pin and at the same time data from the SIOn register is output sequentially to the SOn pin in synchronization with the fall of the serial clock b If an external clock is selected as the serial clock When transmission is started data from the SIOn register is output sequentially to the SOn pin in synchronization with the fall of the serial clock input...

Page 307: ...t register input becomes 0 2 Receiving data in synchronization with the serial clock a If the internal clock is selected as the serial clock When reception is started the serial clock is output from the SCKn pin and at the same time data from the SIn pin is fetched sequentially to the SIOn register in synchronization with the rise of the serial clock b If an external clock is selected as the seria...

Page 308: ...is not started 2 Transmitting data in synchronization with the serial clock a If the internal clock is selected as the serial clock When transmission reception is started the serial clock is output from the SCKn pin and at the same time data from the SIOn register is output sequentially to the SOn pin in synchronization with the fall of the serial clock Also data from the SIn pin is fetched sequen...

Page 309: ...g 3 signal lines the serial clock SCKn serial input SIn and serial output SOn transfer of 8 bit data is carried out This is effective in cases where connections are made to peripheral I O with the old type of clocked serial interface built in or with a display controller etc n 0 to 3 If connecting to multiple devices a line for handshake is necessary Since either the MSB or the LSB can be selected...

Page 310: ...e ASIM00 and ASIM10 registers for UART0 and UART1 and with the CSIM0 to CSIM3 registers for CSI0 to CSI3 If the dedicated baud rate generator output is specified BRG0 to BRG2 are selected as the clock source Since 1 serial clock is used in common for 1 channel of transmission and reception the baud rate is the same for both transmission and for reception Figure 10 11 Block Diagram of Dedicated Bau...

Page 311: ...the following expression bps 2 16 2 j 2 rate Baud k φ φ Internal system clock frequency Hz j Timer count value BRGCn register setting value 1 j 256 Note k Prescaler setting value BPRMn register setting value k 0 1 2 3 4 Note The j 256 setting results in writing 0 to the BRGCn register ii CSI0 to CSI3 If BRG0 to BRG2 are specified as the serial clock source in CSI0 to CSI3 the actual baud rate is e...

Page 312: ... 73 0 3 15 2 Note 153 600 2 457 600 0 3 11 90 Note 0 2 27 2 Note Baud Rate bps φ 40 MHz φ 20 MHz φ 14 764 MHz φ 12 288 MHz UART0 UART1 CSI0 to CSI3 BPR BRG Error BPR BRG Error BPR BRG Error BPR BRG Error 110 1 760 4 178 0 25 4 131 0 07 3 218 0 08 150 2 400 4 130 0 16 3 192 0 0 3 160 0 0 300 4 800 4 130 0 16 3 130 0 16 2 192 0 0 2 160 0 0 600 9 600 4 65 0 16 2 130 0 16 1 192 0 0 1 160 0 0 1 200 19 ...

Page 313: ...e error assuming that both the transmission and reception sides contain an error 10 4 2 Baud rate generator compare registers 0 to 2 BRGC0 to BRGC2 These are 8 bit compare registers used to set the timer count value for the BRG0 to BRG2 These registers can be read written in 8 or 1 bit units Address FFFFF084H 7 BRG07 BRGC0 6 BRG06 5 BRG05 4 BRG04 3 BRG03 2 BRG02 1 BRG01 0 BRG00 After reset Undefin...

Page 314: ...0 00H FFFFF0A6H BRCE2 BPRM2 0 0 0 0 BPR22 BPR21 BPR20 00H Bit Position Bit Name Function 7 BRCEn Baud Rate Generator Count Enable Controls the BRGn count operations 0 Stops count operations in the cleared state 1 Enables the count operation Baud Rate Generator Prescaler Specifies the count clock input to the internal timer TMBRGn BPRn2 BPRn1 BPRn0 Count Clock 0 0 0 φ 2 m 0 0 0 1 φ 4 m 1 0 1 0 φ 8 ...

Page 315: ...t The sample and hold circuit samples each of the analog input signals sequentially sent from the input circuit and sends the sample to the voltage comparator This circuit also holds the sampled analog input signal voltage during A D conversion 3 Voltage comparator The voltage comparator compares the analog input signal with the output voltage of the series resistor string 4 Series resistor string...

Page 316: ...ive approximation register SAR RESET input makes its contents undefined 7 Controller Selects the analog input generates the sample and hold circuit operation timing and controls the conversion trigger according to the mode set to the ADM0 and ADM1 registers 8 ANI0 to ANI7 pins 8 channel analog input pin for the A D converter Inputs the analog signal to be A D converted Caution Make sure that the v...

Page 317: ...in AVREF it may cause an illegal conversion result In order to avoid this illegal conversion result influencing the system software processing is required An example of the necessary software processing is as follows Use the average value of the A D conversion results after obtaining several A D conversion results When an exceptional conversion result is obtained after performing A D conversion se...

Page 318: ...nable Enables or disables A D conversion operation 0 Disabled 1 Enabled 6 CS Converter Status Indicates the status of A D converter This bit is read only 0 Stops 1 Operates 5 BS Buffer Select Specifies buffer mode in the select mode 0 1 buffer mode 1 4 buffer mode 4 MS Mode Select Specifies operation mode of A D converter 0 Scan mode 1 Select mode Analog Input Select Specifies analog input pin to ...

Page 319: ...ode shifts to A D trigger mode after counting the trigger four times and then starts converting Cautions1 When the CE bit is 1 in the timer trigger mode and external trigger mode the trigger signal standby state is set To clear the CE bit write 0 or reset In the A D trigger mode the conversion trigger is set by writing 1 to the CE bit After the operation when the mode is changed to the timer trigg...

Page 320: ...r mode 1 1 0 External trigger mode Other than above Setting prohibited 6 to 4 TRG2 to TRG0 Remark The valid edge of the external input signal during the external trigger mode is specified by bits 7 and 6 ES531 ES530 of the external interrupt mode register INTM6 For details refer to 7 3 8 1 External interrupt mode registers 1 to 6 INTM1 to INTM6 Frequency Specifies conversion operation time These b...

Page 321: ...version results from the ADCRn register only the lower 10 bits are valid and the higher 6 bits are always read as 0 15 0 ADCRn Address FFFFF390H to FFFFF3ACH After reset Undefined 14 0 13 0 12 0 11 0 10 0 9 ADn9 8 ADn8 7 ADn7 6 ADn6 5 ADn5 4 ADn4 3 ADn3 2 ADn2 1 ADn1 0 ADn0 ADCRnH FFFFF392H to FFFFF3AEH Undefined 7 ADn9 6 ADn8 5 ADn7 4 ADn6 3 ADn5 2 ADn4 1 ADn3 0 ADn2 Remark n 0 to 7 The correspon...

Page 322: ...voltage and the A D conversion results Figure 11 2 Relationship Between Analog Input Voltage and A D Conversion Results 1 023 1 022 1 021 3 2 1 0 Input voltage AVREF 1 2 048 1 1 024 3 2 048 2 1 024 5 2 048 3 1 024 2 043 2 048 1 022 1 024 2 045 2 048 1 023 1 024 2 047 2 048 1 A D conversion results ADCRn Remark n 0 to 7 ...

Page 323: ...ring and analog input are compared by the comparator 3 When the comparison of the 10 bits ends the conversion results are stored in the ADCRn register When A D conversion is performed for the specified number of times the A D conversion end interrupt INTAD is generated n 0 to 7 Notes 1 When the ADM0 and ADM1 registers are changed during an A D conversion operation the A D conversion operation befo...

Page 324: ... ANI0 to ANI3 1 Trigger mode There are three types of trigger modes that serve as the start timing of the A D conversion processing A D trigger mode timer trigger mode and external trigger mode The ANI0 to ANI3 pins are able to specify all of these modes but pins ANI4 to ANI7 can only specify the A D trigger mode The timer trigger mode consists of the 1 trigger mode and 4 trigger mode as the sub t...

Page 325: ...ct mode and scan mode The select mode has sub modes including the 1 buffer mode and 4 buffer mode These modes are set by the ADM0 register a Select mode One analog input specified by the ADM0 register is A D converted The conversion results are stored in the ADCRn register corresponding to the analog input ANIn For this mode the 1 buffer mode and 4 buffer mode are provided for storing the A D conv...

Page 326: ...1 Data 7 ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI1 Data 2 ANI1 Data 3 ANI1 Data 4 ANI1 Data 6 ANI1 ADCR1 register INTAD interrupt Conversion start ADM0 register setting Conversion start ADM0 register setting CE bit set CE bit set CE bit set CE bit set CE bit set ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D converter ADCRn regis...

Page 327: ...4 Buffer Mode ANI6 ANI6 input A D conversion Data 1 ANI6 Data 2 ANI6 Data 3 ANI6 Data 4 ANI6 Data 5 ANI6 Data 6 ANI6 Data 7 ANI6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI6 ADCR0 Data 2 ANI6 ADCR1 Data 3 ANI6 ADCR2 Data 4 ANI6 ADCR3 Data 6 ANI6 ADCR0 ADCRn register INTAD interrupt Conversion start ADM0 register setting Conversion start ADM0 register setting ANI0 ANI1 ANI2 ANI3 ANI...

Page 328: ...11 5 Scan Mode Operation Timing 4 Channel Scan ANI0 to ANI3 ANI3 input ANI0 input ANI1 input A D conversion Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 Data 5 ANI0 Data 6 ANI0 Data 7 ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI0 ADCR0 Data 2 ANI1 ADCR1 Data 3 ANI2 ADCR2 Data 4 ANI3 ADCR3 Data 6 ANI0 ADCR0 Conversion start ADM0 register setting Conversion start ADM0 register...

Page 329: ...e conversion results are stored in one ADCRn register The analog input and ADCRn register correspond one to one Each time an A D conversion is executed an INTAD interrupt is generated and the AD conversion terminates Analog Input A D Conversion Results Register ANIn ADCRn n 0 to 7 If 1 is written to the CE bit of the ADM0 register A D conversion can be restarted This is most appropriate for applic...

Page 330: ...he ADM0 register A D conversion can be restarted This is most appropriate for applications that determine the average A D conversion results Figure 11 7 Example of 4 Buffer Mode A D Trigger Select 4 Buffer Operation ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D converter ADM0 4 4 1 CE bit of ADM0 is set to 1 enable 6 ANI4 A D conversion 2 ANI4 A D conv...

Page 331: ...1 is written in the CE bit of the ADM0 register A D conversion can be restarted This is most appropriate for applications that are constantly monitoring multiple analog inputs Figure 11 8 Example of Scan Mode A D Trigger Scan Operation ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D converter ADM0 1 CE bit of ADM0 is set to 1 enable 8 ANI3 A D conversion...

Page 332: ... 1 shot mode When the A D conversion period is longer than the TM11 period the TM11 generates an overflow holds 0000H and stops Thereafter TM11 does not output the match interrupt signal A D conversion trigger of the compare register and the A D converter also enters the A D conversion standby state The TM11 count operation restarts when the valid edge of the TCLR11 pin input is detected or when 1...

Page 333: ...ce using the trigger of the match interrupt signal INTCC110 and the results are stored in one ADCRn register An INTAD interrupt is generated for each A D conversion and A D conversion terminates Trigger Analog Input A D Conversion Result Register INTCC110 interrupt ANIn ADCRn n 0 to 3 When the TM11 is set to the 1 shot mode A D conversion ends after one conversion To restart A D conversion input t...

Page 334: ...e TM11 When the first match interrupt after TM11 is restarted is generated the CS bit is set 1 and A D conversion is started When set to the loop mode unless the CE bit of the ADM0 register is set to 0 A D conversion is repeated each time the match interrupt is generated The match interrupts INTCC110 to INTCC113 can be generated in any order The same trigger even when it enters several times conse...

Page 335: ...lt Register INTCC110 interrupt ANIn ADCR0 INTCC110 interrupt ANIn ADCR1 INTCC110 interrupt ANIn ADCR2 INTCC110 interrupt ANIn ADCR3 n 0 to 3 When the TM11 is set to the 1 shot mode and less than four match interrupts are generated if the CE bit is set to 0 the INTAD interrupt is not generated and the standby state is set Figure 11 11 Example of 1 Trigger Mode Timer Trigger Select 4 Buffer 1 Trigge...

Page 336: ...e loop mode unless the CE bit is set to 0 A D conversion is repeated each time the match interrupt is generated Whichever the order of occurrence of match interrupts INTCC110 to INTCC113 there is no problem and the conversion results are stored in the ADCRn register corresponding to the input trigger Also even in cases where the same trigger is input continuously it is received as a trigger Figure...

Page 337: ...of all the specified analog inputs has ended the INTAD interrupt is generated and A D conversion terminates n 0 to 7 There are two scan modes 1 trigger mode and 4 trigger mode according to the number of triggers This is most appropriate for applications that are constantly monitoring multiple analog inputs 1 1 trigger mode Timer trigger scan 1 trigger The analog inputs are A D converted for the sp...

Page 338: ...ANI1 A D conversion 13 Conversion result is stored in ADCR3 7 Conversion result is stored in ADCR1 14 INTAD interrupt generation Caution The analog input enclosed in the broken lines cannot be used with INTCC11n as the trigger n 0 to 3 When a setting is made to scan ANI0 to ANI7 ANI4 to ANI7 are converted in A D trigger mode see b b Setting when scanning ANI0 to ANI7 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ...

Page 339: ...NTCC110 interrupt ANI0 ADCR0 INTCC111 interrupt ANI1 ADCR1 INTCC112 interrupt ANI2 ADCR2 INTCC113 interrupt ANI3 ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 A D trigger mode ANI7 ADCR7 To restart conversion when TM11 is set to the 1 shot mode restart TM11 If set to the loop mode and the CE bit is 1 A D conversion is restarted when a match interrupt is generated after conversion ends The match interrupt...

Page 340: ... conversion 6 ANI3 A D conversion 13 Conversion result is stored in ADCR2 7 Conversion result is stored in ADCR3 14 INTAD interrupt generation Caution The analog input enclosed in the broken lines cannot be used with INTCC11n as the trigger n 0 to 3 When a setting is made to scan ANI0 to ANI7 ANI4 to ANI7 are converted in A D trigger mode see b b Setting when scanning ANI0 to ANI7 ANI0 ANI1 ANI2 A...

Page 341: ...o the analog input There are two select modes 1 buffer mode and 4 buffer mode storing the conversion results n 0 to 3 1 1 buffer mode External trigger select 1 buffer One analog input is A D converted using the ADTRG signal as a trigger The conversion results are stored in one ADCRn register The analog input and the A D conversion results register correspond one to one INTAD interrupts are generat...

Page 342: ...epeated every time a trigger is input from the ADTRG pin This is most appropriate for applications that determine the average A D conversion results Figure 11 16 Example of 4 Buffer Mode External Trigger Select 4 Buffer Operation ANI0 ANI1 ANI2 ANI3 ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A D converter ADTRG 4 4 1 CE bit of ADM0 is set to 1 enable 8 External trigger generation 2 External t...

Page 343: ... input are set so that they are scanned in the ADM0 register after the conversion of the lower 4 channels ends the mode is shifted to the A D trigger mode and the remaining A D conversions are executed The conversion results are stored in the ADCRn register corresponding to the analog input Trigger Analog Input A D Conversion Result Register ADTRG signal ANI0 ADCR0 ADTRG signal ANI1 ADCR1 ADTRG si...

Page 344: ...ion 6 ANI1 A D conversion 13 Conversion result is stored in ADCR3 7 Conversion result is stored in ADCR1 14 INTAD interrupt generation Caution The analog input enclosed in the broken lines cannot be used with ADTRG as the trigger When a setting is made to scan ANI0 to ANI7 ANI4 to ANI7 are converted in A D trigger mode see b b Setting when scanning ANI0 to ANI7 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 A...

Page 345: ...ted the value at which conversion ended is stored in the ADCRn register 11 8 3 Operation of standby mode 1 HALT mode The A D conversion operation continues When released by the NMI input the ADM0 and ADM1 registers and ADCRn register hold the value n 0 to 7 2 IDLE mode STOP mode As clock supply to the A D converter is stopped no conversion operations are performed When these modes are released usi...

Page 346: ...upts to the CPU b If the TUM15 register s interrupt mask bit IMS153 is 1 The A D converter s external trigger input also functions as an external interrupt to the CPU Figure 11 18 Relationship of A D Converter and Port INTC and RPU P127 INTP153 ADTRG PMC127 PMC12 CMS153 TUM15 CMS11n TUM11 IMS153 TUM15 ES1n1 ES1n0 INTM2 ES531 ES530 INTM6 IMS11n TUM11 TRG0 to TRG2 ADM1 P15MK3 P15IC3 P11MKn P11ICn A ...

Page 347: ...M00 347 CHAPTER 12 PORT FUNCTIONS 12 1 Features Number of ports Input only ports 9 I O ports 114 Function alternately as the input output pins of other peripheral functions It is possible to specify input and output in bit units ...

Page 348: ...med ports 0 through 12 and A B and X The port configuration is shown below Port 0 P00 to P07 Port 1 P10 to P17 Port 2 P21 to P27 P20 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P67 Port 8 Port 9 P80 to P87 P90 to P97 Port 10 Port 11 Port 12 Port A P100 to P107 P110 to P117 P120 to P127 PA0 to PA7 Port B PB0 to PB7 Port 7 P70 to P77 Port X PX5 PX6 PX7 ...

Page 349: ... input G Port 8 P80 to P87 8 bit I O External bus interface control signal output O P Port 9 P90 to P97 8 bit I O External bus interface control signal input output H O Port 10 P100 to P107 8 bit I O Input output of real time pulse unit RPU External interrupt input DMA control DMAC output A B K Port 11 P110 to P117 8 bit I O Input output of real time pulse unit RPU External interrupt input Serial ...

Page 350: ...ode P11 TO111 P11 input mode P12 TCLR11 P12 input mode P13 TI11 P13 input mode PMC1 P14 INTP110 DMAAK0 P14 input mode P15 INTP111 DMAAK1 P15 input mode P16 INTP112 DMAAK2 P16 input mode Port 1 P17 INTP113 DMAAK3 P17 input mode PMC1 PCS1 Note P20 NMI NMI P21 P21 input mode P22 TXD0 SO0 P22 input mode P23 RXD0 SI0 P23 input mode PMC2 ASIM00 P24 SCK0 P24 input mode PMC2 Note P25 TXD1 SO1 P25 input mo...

Page 351: ...mode CS3 RAS3 PMC8 P84 CS4 RAS4 IOWR P84 input mode CS4 RAS4 P85 CS5 RAS5 IORD P85 input mode CS5 RAS5 PMC8 PCS8 Note P86 CS6 RAS6 P86 input mode CS6 RAS6 Port 8 P87 CS7 RAS7 P87 input mode CS7 RAS7 PMC8 P90 LCAS LWR P90 input mode LCAS LWR P91 UCAS UWR P91 input mode UCAS UWR P92 RD P92 input mode RD P93 WE P93 input mode WE PMC9 P94 BCYST P94 input mode BCYST PMC9 P95 OE P95 input mode OE P96 HL...

Page 352: ...input mode Port 11 P117 INTP143 SCK3 P117 input mode PMC11 PCS11 Note P120 TO150 P120 input mode P121 TO151 P121 input mode P122 TCLR15 P122 input mode P123 TI15 P123 input mode P124 INTP150 P124 input mode P125 INTP151 P125 input mode P126 INTP152 P126 input mode PMC12 Port 12 P127 INTP153 ADTRG P127 input mode PMC12 ADM1 Note Port A PA0 A0 to PA7 A7 PA0 to PA7 input mode A0 to A7 MM Port B PB0 A...

Page 353: ...anual U12688EJ4V0UM00 353 3 Block diagram of port Figure 12 1 Type A Block Diagram Internal bus WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Selector Selector Selector Pmn Address Remark m Port number n Bit number ...

Page 354: ...anual U12688EJ4V0UM00 354 Figure 12 2 Type B Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Selector Selector Pmn Address Noise elimination edge detection Input signal in control mode Internal bus Remark m Port number n Bit number ...

Page 355: ... 355 Figure 12 3 Type C Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Output signal in control mode SCKx output enable signal Internal bus Selector Selector Selector Remark mn 24 27 x 0 when mn 24 1 when mn 27 ...

Page 356: ...UNCTIONS User s Manual U12688EJ4V0UM00 356 Figure 12 4 Type D Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Internal bus Selector Selector Remark m Port number n Bit number ...

Page 357: ...UM00 357 Figure 12 5 Type E Block Diagram WRPM WRPORT RDIN PMmn Pmn Pmn Address MODE0 to MODE3 MM0 to MM3 I O controller Input signal in control mode Output signal in control mode Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 358: ...RPORT RDIN PMmn Pmn Pmn MODE0 to MODE3 MM0 to MM3 Address I O controller Output signal in control mode Internal bus Selector Selector Selector Remark m Port number n Bit number Figure 12 7 Type G Block Diagram RDIN P7n ANIn Sample hold circuit Input signal in control mode Internal bus Remark n 0 to 7 ...

Page 359: ...8 Type H Block Diagram WRPM WRPORT RDIN PMmn Pmn P97 MODE0 to MODE3 MM0 to MM3 Address I O controller Input signal in control mode Internal bus Selector Selector Figure 12 9 Type I Block Diagram RDIN P20 Address Noise elimination Edge detection 1 NMI Internal bus Selector ...

Page 360: ...CHAPTER 12 PORT FUNCTIONS User s Manual U12688EJ4V0UM00 360 Figure 12 10 Type J Block Diagram WRPM WRPORT RDIN PMmn Pmn Pmn Address Internal bus Selector Selector Remark m Port number n Bit number ...

Page 361: ...Figure 12 11 Type K Block Diagram WRPCS WRPMC WRPM WRPORT RDIN PCSmn PMCmn PMmn Pmn Pmn Address Noise elimination edge detection Selector Selector Selector Input signal in control mode Output signal in control mode Internal bus Remark m Port number n Bit number ...

Page 362: ...NCTIONS User s Manual U12688EJ4V0UM00 362 Figure 12 12 Type L Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Internal bus Selector Selector Remark m Port number n Bit number ...

Page 363: ...ype M Block Diagram WRPCS WRPMC WRPM WRPORT RDIN PCSmnNote PMCmn PMmn Pmn Pmn INTP100 to INTP103 INTP132 INTP142 DMARQ0 to DMARQ3 SI2 SI3 Address Noise elimination edge detection Internal bus Selector Selector Note When mn 36 PCS35 When mn 116 PCS115 Remark mn 04 to 07 36 116 ...

Page 364: ... N Block Diagram WRPCS WRPMC WRPM WRPORT RDIN PCSm5 PMCmn PMmn Pmn Pmn INTP133 INTP143 SCK2 SCK3 SCKx output enable signal Address Noise elimination edge detection Output signal in control mode Internal bus Selector Selector Selector Remark mn 37 117 x 2 when mn 37 3 when mn 117 ...

Page 365: ...688EJ4V0UM00 365 Figure 12 15 Type O Block Diagram WRPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn MODE0 to MODE3 MM0 to MM3 Address I O controller Output signal in control mode Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 366: ...0 366 Figure 12 16 Type P Block Diagram MODE0 to MODE3 MM0 to MM3 WRPCS WRPMC WRPM WRPORT RDIN PCSmn PMCmn PMmn Pmn Pmn Address I O controller Output signal in control mode Internal bus Selector Selector Selector Selector Remark m Port number n Bit number ...

Page 367: ...al U12688EJ4V0UM00 367 Figure 12 17 Type Q Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Output signal in control mode Serial output enable signal Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 368: ...pe P00 TO100 P01 TO101 Real time pulse unit RPU output A P02 TCLR10 P03 TI10 Real time pulse unit RPU input B Port 0 P04 to P07 INTP100 DMARQ0 to INTP103 DMARQ3 External interrupt request input DMA request input M 2 Input output mode control mode setting Port 0 input output mode setting is performed by means of the port 0 mode register PM0 and control mode setting is performed by means of the port...

Page 369: ...s in combination with the PCS0 register 0 Input output port mode 1 External interrupt request INTP103 to INTP100 input mode DMA request DMARQ3 to DMARQ0 input mode 3 PMC03 Port Mode Control Sets operation mode of P03 pin 0 Input output port mode 1 TI10 input mode 2 PMC02 Port Mode Control Sets operation mode of P02 pin 0 Input output port mode 1 TCLR10 input mode 1 PMC01 Port Mode Control Sets ope...

Page 370: ...rating mode when pin P07 is in the control mode 0 INTP103 input mode 1 DMARQ3 input mode 6 PCS06 Port Control Select Specifies the operating mode when pin P06 is in the control mode 0 INTP102 input mode 1 DMARQ2 Input mode 5 PCS05 Port Control Select Specifies the operating mode when pin P05 is in the control mode 0 INTP101 input mode 1 DMARQ1 input mode 4 PCS04 Port Control Select Specifies the o...

Page 371: ... P10 TO110 P11 TO111 Real time pulse unit RPU output A P12 TCLR11 P13 TI11 Real time pulse unit RPU input B Port 1 P14 to P17 INTP110 DMAAK0 to INTP113 DMAAK3 External interrupt input DMA acknowledge output K 2 Input output mode control mode setting Port 1 input output mode setting is performed by means of the port 1 mode register PM1 and control mode setting is performed by means of the port 1 mo...

Page 372: ... in combination with PCS1 0 Input output port mode 1 External interrupt request INTP113 to INTP110 input mode DMA acknowledge DMAAK3 to DMAAK0 output mode 3 PMC13 Port Mode Control Sets operation mode of P13 pin 0 Input output port mode 1 TI11 input mode 2 PMC12 Port Mode Control Sets operation mode of P12 pin 0 Input output port mode 1 TCLR11 input mode 1 PMC11 Port Mode Control Sets operation mo...

Page 373: ...ting mode when pin P17 is in the control mode 0 INTP113 input mode 1 DMAAK3 output mode 6 PCS16 Port Control Select Specifies the operating mode when pin P16 is in the control mode 0 INTP112 input mode 1 DMAAK2 output mode 5 PCS15 Port Control Select Specifies the operating mode when pin P15 is in the control mode 0 INTP111 input mode 1 DMAAK1 output mode 4 PCS14 Port Control Select Specifies the ...

Page 374: ...t 2 Input output port 0 P20 Fix to NMI input mode In addition to their function as port pins the port 2 pins can also operate as serial interface UART0 CSI0 UART1 CSI1 inputs outputs in the control mode Note that pin P21 does not have an alternate function and operates only in the port mode 1 Operation in control mode Port Control Mode Remark Block Type P20 NMI Non maskable interrupt request input...

Page 375: ...ten in 8 or 1 bit units However bit 0 is fixed at 1 by hardware so writing 0 to this bit is ignored Address FFFFF024H 7 PM27 PM2 6 PM26 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 1 After reset FFH Bit Position Bit Name Function 7 to 1 PM2n n 7 to 1 Port Mode Sets P2n in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF Caution When the serial interface is used use the follo...

Page 376: ...ode 6 PMC26 Port Mode Control Sets operation mode of P26 pin 0 Input output port mode 1 RXD1 SI1 input mode 5 PMC25 Port Mode Control Sets operation mode of P25 pin 0 Input output port mode 1 TXD1 SO1 output mode 4 PMC24 Port Mode Control Sets operation mode of P24 pin 0 Input output port mode 1 SCK0 input output mode 3 PMC23 Port Mode Control Sets operation mode of P23 pin 0 Input output port mod...

Page 377: ...n as port pins the port 3 pins can also operate as the input output signals of the real time pulse unit RPU the input signals of external interrupt and the input output lines of the serial interface CSI2 when in the control mode 1 Operation in control mode Port Control Mode Remark Block Type P30 TO130 P31 TO131 Real time pulse unit RPU output A P32 TCLR13 P33 TI13 Real time pulse unit RPU input P3...

Page 378: ...rmed by means of the port 3 mode control register PMC3 and port control select register 3 PCS3 a Port 3 mode register PM3 This register can be read written in 8 or 1 bit units Address FFFFF026H 7 PM37 PM3 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 After reset FFH Bit Position Bit Name Function 7 to 0 PM3n n 7 to 0 Port Mode Sets P3n in input output mode 0 Output mode output buffer ON 1 Input...

Page 379: ...ode 1 External interrupt request INTP133 to INTP131 input mode CSI2 SCK2 SI2 SO2 input output mode 4 PMC34 Port Mode Control Sets operation mode of P34 pin 0 Input output port mode 1 INTP130 input mode 3 PMC33 Port Mode Control Sets operation mode of P33 pin 0 Input output port mode 1 TI13 input mode 2 PMC32 Port Mode Control Sets operation mode of P32 pin 0 Input output port mode 1 TCLR13 input m...

Page 380: ...CK2 input output mode P37 SI2 input mode P36 SO2 output mode P35 Caution When the port mode is specified by the PMC3 register the settings of this register are ignored 12 3 5 Port 4 Port 4 is an 8 bit input output port that can be set to input or output in 1 bit units Address FFFFF008H 7 P47 P4 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 After reset Undefined Bit Position Bit Name Function 7 to 0 P4...

Page 381: ... 7 to 0 PM4n n 7 to 0 Port Mode Sets P4n in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF b Operation mode of port 4 Bit of MM Register Operation Mode MM3 MM2 MM1 MM0 P40 P41 P42 P43 P44 P45 P46 P47 0 0 0 Port P40 to P47 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 don t care 1 1 1 Data bus D0 to D7 For the details of mode selection by the MODE0 to MODE3 pins refer to 3 3 ...

Page 382: ... 2 P52 1 P51 0 P50 After reset Undefined Bit Position Bit Name Function 7 to 0 P5n n 7 to 0 Port 5 Input output port In addition to their function as port pins the port 5 pins can also operate in the control mode external expansion mode as a data bus used when memory is expanded externally 1 Operation in control mode Port Control Mode Remark Block Type Port 5 P50 to P57 D8 to D15 Data bus in memor...

Page 383: ...to 0 Port Mode Sets P5n in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF b Operation mode of port 5 Bit of MM Register Operation Mode MM3 MM2 MM1 MM0 P50 P51 P52 P53 P54 P55 P56 P57 0 0 0 0 Port P50 to P57 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 Data bus D8 to D15 1 don t care Port 50 to P57 For the details of mode selection by the MODE0 to MODE3 p...

Page 384: ...62 1 P61 0 P60 After reset Undefined Bit Position Bit Name Function 7 to 0 P6n n 7 to 0 Port 6 Input output port In addition to their function as port pins the port 6 pins can also operate in the control mode external expansion mode as an address bus used when memory is expanded externally 1 Operation in control mode Port Control Mode Remark Block Type Port 6 P60 to P67 A16 to A23 Address bus in m...

Page 385: ...ition Bit Name Function 7 to 0 PM6n n 7 to 0 Port Mode Sets P6n in input output mode 0 Output mode output buffer ON 1 Input mode output buffer OFF b Operation mode of port 6 Bit of MM Register Operation Mode MM3 MM2 MM1 MM0 P60 P61 P62 P63 P64 P65 P66 P67 0 0 0 0 0 1 0 1 0 0 1 1 Port P60 to P67 1 0 0 P62 P63 1 0 1 P64 P65 1 1 0 P66 P67 don t care 1 1 1 A16 A17 A18 A19 A20 A21 A22 A23 For the detai...

Page 386: ... After reset Undefined In addition to their function as port pins the port 7 pins can also operate as analog inputs for A D converter This port is used also as the analog input pins ANI0 to ANI7 but the port and analog input pins cannot be switched By reading the port the state of each pin can be read 1 Operation in control mode Port Control Mode Remark Block Type Port 7 P70 to P77 ANI0 to ANI7 An...

Page 387: ...mode the port 8 pins operate as chip select signal outputs row address strobe signal outputs for DRAM and read write strobe signal outputs for external I O 1 Operation in control mode Port Control Mode Remark Block Type P80 to P83 CS0 RAS0 to CS3 RAS3 Chip select signal output Row address signal output O P84 CS4 RAS4 IOWR Chip select signal output Row address signal output Write strobe signal outp...

Page 388: ... performed by means of the mode specification pins MODE0 to MODE3 and the port 8 mode control register PMC8 a Port 8 mode register PM8 This register can be read written in 8 or 1 bit units Address FFFFF030H 7 PM87 PM8 6 PM86 5 PM85 4 PM84 3 PM83 2 PM82 1 PM81 0 PM80 After reset FFH Bit Position Bit Name Function 7 to 0 PM8n n 7 to 0 Port Mode Sets P8n pin in input output mode 0 Output mode output ...

Page 389: ... 1 CS6 RAS6 output mode 5 PMC85 Port Mode Control Sets operation mode of P85 pin Set in combination with PCS8 0 Input output port mode 1 CS5 RAS5 output mode IORD output mode 4 PMC84 Port Mode Control Sets operation mode of P84 pin Set in combination with PCS8 0 Input output port mode 1 CS4 RAS4 output mode IOWR output mode 3 PMC83 Port Mode Control Sets operation mode of P83 pin 0 Input output po...

Page 390: ...FFFF590H After reset 00H 1 0 2 0 3 0 4 PCS84 5 PCS85 6 0 7 0 PCS8 Bit Position Bit Name Function 5 PCS85 Port Control Select Specifies the operating mode when pin P85 is in the control mode 0 CS5 RAS5 output mode 1 IORD output mode 4 PCS84 Port Control Select Specifies the operating mode when pin P84 is in the control mode 0 CS4 RAS4 output mode 1 IOWR output mode Caution When the port mode is spe...

Page 391: ... Port 9 Input output port In addition to their function as port pins the port 9 pins can also operate in the control mode external expansion mode as control signal outputs and bus hold control signal output used when memory is expanded externally 1 Operation in control mode Port Control Mode Remark Block Type P90 LWR LCAS P91 UWR UCAS P92 RD P93 WE P94 BCYST P95 OE Control signal output in memory ...

Page 392: ... performed by means of the mode specification pins MODE0 to MODE3 and the port 9 mode control register PMC9 a Port 9 mode register PM9 This register can be read written in 8 or 1 bit units Address FFFFF032H 7 PM97 PM9 6 PM96 5 PM95 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90 After reset FFH Bit Position Bit Name Function 7 to 0 PM9n n 7 to 0 Port Mode Sets P9n pin in input output mode 0 Output mode output ...

Page 393: ... Sets operation mode of P96 pin 0 Input output port mode 1 HLDAK output mode 5 PMC95 Port Mode Control Sets operation mode of P95 pin 0 Input output port mode 1 OE output mode 4 PMC94 Port Mode Control Sets operation mode of P94 pin 0 Input output port mode 1 BCYST output mode 3 PMC93 Port Mode Control Sets operation mode of P93 pin 0 Input output port mode 1 WE output mode 2 PMC92 Port Mode Contr...

Page 394: ...20 P101 TO121 Real time pulse unit RPU output A P102 TCLR12 P103 TI12 Real time pulse unit RPU input B Port 10 P104 to P107 INTP120 TC0 to INTP123 TC3 External interrupt input DMA terminal count output K 2 Input output mode control mode setting Port 10 input output mode setting is performed by means of the port 10 mode register PM10 and control mode setting is performed by means of the port 10 mod...

Page 395: ...Set in combination with PCS10 0 Input output port mode 1 External interrupt request INTP123 to INTP120 input mode DMA terminal signal TC3 to TC0 output mode 3 PMC103 Port Mode Control Sets operation mode of P103 pin 0 Input output port mode 1 TI12 input mode 2 PMC102 Port Mode Control Sets operation mode of P102 pin 0 Input output port mode 1 TCLR12 input mode 1 PMC101 Port Mode Control Sets opera...

Page 396: ... operating mode when pin P107 is in the control mode 0 INTP123 input mode 1 TC3 output mode 6 PCS106 Port Control Select Specifies the operating mode when pin P106 is in the control mode 0 INTP122 input mode 1 TC2 output mode 5 PCS105 Port Control Select Specifies the operating mode when pin P105 is in the control mode 0 INTP121 input mode 1 TC1 output mode 4 PCS104 Port Control Select Specifies t...

Page 397: ...dition to their function as port pins the port 11 pins can also operate as real time pulse unit RPU inputs outputs external interrupt request inputs and serial interface CSI3 inputs outputs in the control mode 1 Operation in control mode Port Control Mode Remark Block Type P110 TO140 P111 TO141 Real time pulse unit RPU output A P112 TCLR14 P113 TI14 Real time pulse unit RPU input P114 INTP140 Exte...

Page 398: ...eans of the port 11 mode control register PMC11 and port control select register 11 PCS11 a Port 11 mode register PM11 This register can be read written in 8 or 1 bit units Address FFFFF036H 7 PM117 PM11 6 PM116 5 PM115 4 PM114 3 PM113 2 PM112 1 PM111 0 PM110 After reset FFH Bit Position Bit Name Function 7 to 0 PM11n n 7 to 0 Port Mode Sets P11n pin in input output mode 0 Output mode output buffe...

Page 399: ... mode 1 External interrupt request INTP143 to INTP141 input mode CSI3 SCK3 SI3 SO3 input output mode 4 PMC114 Port Mode Control Sets operation mode of P114 pin 0 Input output port mode 1 INTP140 input mode 3 PMC113 Port Mode Control Sets operation mode of P113 pin 0 Input output port mode 1 TI14 input mode 2 PMC112 Port Mode Control Sets operation mode of P112 pin 0 Input output port mode 1 TCLR14...

Page 400: ...ress FFFFF596H After reset 00H 1 0 2 0 3 0 4 0 5 PCS115 6 0 7 0 PCS11 Bit Position Bit Name Function 5 PCS115 Port Control Select Specifies the operating mode when pins P117 to P115 are in the control mode 0 INTP143 input mode P117 INTP142 input mode P116 INTP141 input mode P115 1 SCK3 input output mode P117 SI3 input mode P116 SO3 output mode P115 Caution When the port mode is specified by the PM...

Page 401: ... TO150 P121 TO151 Real time pulse unit RPU output A P122 TCLR15 P123 TI15 Real time pulse unit RPU input P124 to P126 INTP150 to INTP152 External interrupt input Port 12 P127 INTP153 ADTRG External interrupt input AD converter external trigger input B 2 Input output mode control mode setting Port 12 input output mode setting is performed by means of the port 12 mode register PM12 and control mode ...

Page 402: ... Control Sets operation mode of P12n pin 0 Input output port mode 1 External interrupt request INTP152 to INTP150 input mode 3 PMC123 Port Mode Control Sets operation mode of P123 pin 0 Input output port mode 1 TI15 input mode 2 PMC122 Port Mode Control Sets operation mode of P122 pin 0 Input output port mode 1 TCLR15 input mode 1 PMC121 Port Mode Control Sets operation mode of P121 pin 0 Input ou...

Page 403: ...e Port Control Mode Remark Block Type Port A PA0 to PA7 A0 to A7 Address bus in memory expansion F 2 Input output mode control mode setting Port A input output mode setting is performed by means of the port A mode register PMA and control mode external expansion mode setting is performed by means of the mode specification pins MODE0 to MODE3 and the memory expansion mode register MM refer to 3 4 6...

Page 404: ... 1 Address bus A0 to A7 For the details of mode selection by the MODE0 to MODE3 pins refer to 3 3 2 Operating mode specification In ROM less modes 0 or 1 or single chip mode 1 the MM0 to MM3 bits are initialized to 111 at system reset enabling the external address output mode If MM0 to MM3 are set to 000 by the program the port mode can be changed to but the subsequent external instruction cannot ...

Page 405: ... Port Control Mode Remark Block Type Port B PB0 to PB7 A8 to A15 Address bus in memory expansion F 2 Input output mode control mode setting Port B input output mode setting is performed by means of the port B mode register PMB and control mode external expansion mode setting is performed by means of the mode specification pins MODE0 to MODE3 and the memory expansion mode register MM refer to 3 4 6...

Page 406: ...of mode selection by the MODE0 to MODE3 pins refer to 3 3 2 Operating mode specification In ROM less modes 0 or 1 or single chip mode 1 the MM0 to MM3 bits are initialized to 111 at system reset enabling the external address output mode If MM0 to MM3 are set to 000 by the program the port mode can be changed to but the subsequent external instruction cannot be fetched from data bus Also if MM0 to ...

Page 407: ...5 REFRQ DRAM refresh request signal output A PX6 WAIT Wait control input L Port X PX7 CLKOUT Internal system clock output A 2 Input output mode control mode setting Port X input output mode setting is performed by means of the port X mode register PMX and control mode setting is performed by means of the port X mode control register PMCX a Port X mode register PMX This register is write only in 8 ...

Page 408: ... Note Note Single chip mode 0 00H Single chip mode 1 E0H ROM less mode 0 1 E0H Bit Position Bit Name Function 7 PMCX7 Port Mode Control Sets operation mode of PX7 pin 0 Input output port mode 1 CLKOUT output mode 6 PMCX6 Port Mode Control Sets operation mode of PX6 pin 0 Input output port mode 1 WAIT input mode 5 PMCX5 Port Mode Control Sets operation mode of PX5 pin 0 Input output port mode 1 REF...

Page 409: ...ister is connected there memory contents may be lost when these pins enter high impedance state For the same reason the output pins of the internal peripheral I O functions and output ports should be handled in the same manner Note In ROM less modes 0 and 1 and in single chip mode 1 the CLKOUT signal is output even during reset In single chip mode 0 the CLKOUT signal is not output until the PMCX r...

Page 410: ... width of the RESET signal it is necessary to secure an oscillation stabilization time of 10 ms or greater from power rise to the reception of the reset HVDD RESET input Oscillation stabilization time Analog delay Reset release 13 3 Initialization The initial values of the CPU internal RAM and internal peripheral I O after reset are shown in Table 13 2 Initialize the contents of each register as n...

Page 411: ...ion register BCT 0000H Bus control functions Bus size configuration register BSC 5555H 0000H DRAM configuration registers DRC0 to DRC3 3FC1H DRAM type configuration register DTC 0000H Page ROM configuration register PRC E0H Refresh control registers RFC0 to RFC3 0000H Memory control functions Refresh wait control register RWC 00H Control registers DADC0 to DADC3 0000H Source address registers DSA0...

Page 412: ...RXB1 RXB0L RXB1L Undefined Transmit shift registers TXS0 TXS1 TXS0L TXS1L Undefined Clocked serial interface mode registers CSIM0 to CSIM3 00H Serial I O shift registers SIO0 to SIO3 Undefined Baud rate generator compare registers BRGC0 to BRGC2 Undefined Serial interface functions Baud rate generator prescaler mode registers BPRM0 to BPRM2 00H Mode register ADM0 00H Mode register ADM1 07H A D con...

Page 413: ...by differentiating software Data adjustment in starting mass production is made easier 14 1 Features 4 byte 1 clock access in instruction fetch access All area one shot erase Erase in 4KB block units Communication through serial interface from the dedicated flash programmer Erase write voltage VPP 7 8 V On board programming Number of rewrites 100 times target 14 2 Writing by Flash Programmer Writi...

Page 414: ...grammer UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850E MS1 to perform writing erasing etc A dedicated program adapter FA Series is required for off board writing 14 4 Communication System 1 UART0 Transfer rate 4 800 to 76 800 bps LSB first V850E MS1 Dedicated flash programmer VPP VDD VSS RESET TXD0 RXD0 Clock 2 CSI0 Transfer rate up to 10 Mbps MSB firs...

Page 415: ...mal operation mode 0 V is input to the MODE3 VPP pin In the flash memory programming mode 7 8 V writing voltage is supplied to the MODE3 VPP pin The following shows an example of the connection of the MODE3 VPP pin V850E MS1 MODE3 VPP Pull down resistor RVPP Dedicated flash programmer connection pin 14 5 2 Serial interface pin The following shows the pins used by each serial interface Serial Inter...

Page 416: ...output connected to another device input the signal output to the other device may cause the device to malfunction To avoid this isolate the connection to the other device or make the setting so that the input signal to the other device is ignored V850E MS1 Output pin Input pin Other device Dedicated flash programmer connection pin In the flash memory programming mode if the signal the V850E MS1 o...

Page 417: ...als on the reset signal generator side 14 5 4 NMI pin Do not change the input signal to the NMI pin during the flash memory programming mode If the NMI pin is changed during the flash memory programming mode the programming may not be performed correctly 14 5 5 MODE0 to MODE2 pins If MODE0 to MODE2 are set as follows and a write voltage 7 8 V is applied to the MODE3 VPP pin and reset is canceled t...

Page 418: ...Connect VDD and GND of the dedicated flash programmer to VDD and VSS VDD of the dedicated flash programmer is provided with power supply monitoring function 14 6 Programming Method 14 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Start Switch to flash memory programming mode Supply RESET pulse Select communication system Manipulate flash memory End En...

Page 419: ... 3 V 0 V RESET 2 Remark don t care 14 6 3 Selection of communication mode In the V850E MS1 a communication mode is selected by inputting pulses 16 pulses max to VPP pin after switching to the flash memory programming mode The VPP pulse is generated by the dedicated flash programmer The following shows the relationship between the number of pulses and the communication modes Table 14 1 List of Comm...

Page 420: ...tire memory Block erase command Erases the contents of the specified memory block setting 4 Kbytes as one memory block Erase Write back command Writes back the contents that is over erased One shot blank check command Checks the erase state of the entire memory Blank check Block blank check command Checks the erase of the specified memory block High speed write command Writes data by the specifica...

Page 421: ...E MS1 sends back response commands to the commands issued from the dedicated flash programmer The following shows the response commands the V850E MS1 sends out Response Command Name Function ACK acknowledge Acknowledges command data etc NAK not acknowledge Acknowledges illegal command data etc ...

Page 422: ...User s Manual U12688EJ4V0UM00 422 MEMO ...

Page 423: ... A D conversion result register 7H ADC 321 ADIC Interrupt control register INTC 217 ADM0 A D converter mode register 0 ADC 318 ADM1 A D converter mode register 1 ADC 320 ASIM00 Asynchronous serial interface mode register 00 UART0 287 ASIM01 Asynchronous serial interface mode register 01 UART0 290 ASIM10 Asynchronous serial interface mode register 10 UART1 287 ASIM11 Asynchronous serial interface m...

Page 424: ...apture compare register 133 RPU 252 CC140 Capture compare register 140 RPU 252 CC141 Capture compare register 141 RPU 252 CC142 Capture compare register 142 RPU 252 CC143 Capture compare register 143 RPU 252 CC150 Capture compare register 150 RPU 252 CC151 Capture compare register 151 RPU 252 CC152 Capture compare register 152 RPU 252 CC153 Capture compare register 153 RPU 252 CKC Clock control re...

Page 425: ...70 DCHC2 DMA channel control register 2 DMAC 170 DCHC3 DMA channel control register 3 DMAC 170 DDA0H DMA destination address register 0H DMAC 165 DDA0L DMA destination address register 0L DMAC 166 DDA1H DMA destination address register 1H DMAC 165 DDA1L DMA destination address register 1L DMAC 166 DDA2H DMA destination address register 2H DMAC 165 DDA2L DMA destination address register 2L DMAC 166...

Page 426: ...terrupt CPU 72 EIPSW Status saving register during interrupt CPU 72 FDW Flyby transfer data wait control register BCU 174 FEPC Status saving register during NMI CPU 72 FEPSW Status saving register during NMI CPU 72 INTM0 External interrupt mode register 0 INTC 208 INTM1 External interrupt mode register 1 INTC 221 INTM2 External interrupt mode register 2 INTC 221 INTM3 External interrupt mode regis...

Page 427: ...control register INTC 217 P12 Port 12 Port 401 P12IC0 Interrupt control register INTC 217 P12IC1 Interrupt control register INTC 217 P12IC2 Interrupt control register INTC 217 P12IC3 Interrupt control register INTC 217 P13IC0 Interrupt control register INTC 217 P13IC1 Interrupt control register INTC 217 P13IC2 Interrupt control register INTC 217 P13IC3 Interrupt control register INTC 217 P14IC0 In...

Page 428: ...de register Port 392 PM10 Port 10 mode register Port 394 PM11 Port 11 mode register Port 398 PM12 Port 12 mode register Port 401 PMA Port A mode register Port 403 PMB Port B mode register Port 405 PMC0 Port 0 mode control register Port 369 PMC1 Port 1 mode control register Port 372 PMC2 Port 2 mode control register Port 376 PMC3 Port 3 mode control register Port 379 PMC8 Port 8 mode control regist...

Page 429: ...ter 1 CSI1 303 SIO2 Serial I O shift register 2 CSI2 303 SIO3 Serial I O shift register 3 CSI3 303 SRIC0 Interrupt control register INTC 217 SRIC1 Interrupt control register INTC 217 STIC0 Interrupt control register INTC 217 STIC1 Interrupt control register INTC 217 SYS System status register CPU 102 TM10 Timer 10 RPU 251 TM11 Timer 11 RPU 251 TM12 Timer 12 RPU 251 TM13 Timer 13 RPU 251 TM14 Timer...

Page 430: ...r 15 RPU 260 TOVS Timer overflow status register RPU 261 TUM10 Timer unit mode register 10 RPU 254 TUM11 Timer unit mode register 11 RPU 254 TUM12 Timer unit mode register 12 RPU 254 TUM13 Timer unit mode register 13 RPU 254 TUM14 Timer unit mode register 14 RPU 254 TUM15 Timer unit mode register 15 RPU 254 TXS0 Transmit shift register 0 9 bits UART0 293 TXS0L Transmit shift register 0L Lower orde...

Page 431: ...ich specify the trap vector 00H to 1FH listX X item register list 2 Register symbols used to describe op codes Register Symbol Explanation R 1 bit data of a code which specifies reg1 or regID r 1 bit data of the code which specifies reg2 w 1 bit data of the code which specifies reg3 d 1 bit displacement data i 1 bit immediate data cccc 4 bit data which show the conditions code bbb 3 bit data for s...

Page 432: ...uct OR Logical sum XOR Exclusive OR NOT Logical negation logically shift left by Logical shift left logically shift right by Logical shift right arithmetically shift right by Arithmetic shift right 4 Register symbols used in an execution clock Register Symbol Explanation i issue If executing another instruction immediately after executing the first instruction r repeat If repeating execution of th...

Page 433: ... lower Greater than or equal Z E 0 0 1 0 Z 1 Zero Equal NZ NE 1 0 1 0 Z 0 Not zero Not equal NH 0 0 1 1 CY or Z 1 Not higher Less than or equal H 1 0 1 1 CY or Z 0 Higher Greater than N 0 1 0 0 S 1 Negative P 1 1 0 0 S 0 Positive T 0 1 0 1 Always Unconditional SA 1 1 0 1 SAT 1 Saturated LT 0 1 1 0 S xor OV 1 Less than signed GE 1 1 1 0 S xor OV 0 Greater than or equal signed LE 0 1 1 1 S xor OV or...

Page 434: ...r 11 1 1 11 0 0 00 0 wwwww01101000000 GR reg3 GR reg2 7 0 ll GR reg2 15 8 ll GR reg2 23 16 ll GR reg2 31 24 1 1 1 0 CALLT imm6 0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC PC 2 return PC CTPSW PSW adr CTBP zero extend imm6 logically shift left by 1 PC CTBP zero extend Load memory adr Half word 4 4 4 bit 3 disp16 reg1 10bbb111110RRRRR dddddddddddddddd adr GR reg1 sign extend disp16 Z flag Not Load memory b...

Page 435: ...2 GR reg1 35 35 35 DIVHU reg1 reg2 reg3 rrrrr111111RRRRR wwwww01010000010 GR reg2 GR reg2 GR reg1 Note 6 GR reg3 GR reg2 GR reg1 34 34 34 DIVU reg1 reg2 reg3 rrrrr111111RRRRR wwwww01011000010 GR reg2 GR reg2 GR reg1 GR reg3 GR reg2 GR reg1 34 34 34 EI 1000011111100000 0000000101100000 PSW ID 0 1 1 1 HALT 0000011111100000 0000000100100000 Stop 1 1 1 HSW reg2 reg3 r rr r r 11 1 1 11 0 0 00 0 wwwww01...

Page 436: ...R wwwww01000100000 GR reg3 ll GR reg2 GR reg2 xGR reg1 1 2 Note14 2 MUL imm9 reg2 reg3 r r r r r 1 1 1 1 1 1 i i i i i wwwww01001llll00 GR reg3 ll GR reg2 GR reg2 xsign extend imm9 Note 13 1 2 Note14 2 reg1 reg2 rrrrr000111RRRRR GR reg2 GR reg2 Note 6 xGR reg1 Note 6 1 1 2 MULH imm5 reg2 r r r r r 0 1 0 1 1 1 i i i i i GR reg2 GR reg2 Note 6 xsign extend imm5 1 1 2 MULHI imm16 reg1 reg2 rrrrr11011...

Page 437: ...C PSW FEPSW else PC EIPC PSW EIPSW 3 3 3 R R R R R reg1 reg2 rrrrr111111RRRRR 0000000010100000 GR reg2 GR reg2 arithmetically shift right by GR reg1 1 1 1 0 SAR imm5 reg2 r r r r r 0 1 0 1 0 1 i i i i i GR reg2 GR reg2 arithmetically shift right by zero extend imm5 1 1 1 0 SASF cccc reg2 r r r r r 1 1 1 1 1 1 0 c c c c 0000001000000000 if conditions are satisfied then GR reg2 GR reg2 Logically shi...

Page 438: ...o extend disp4 GR reg2 zero extend Load memory adr Byte 1 1 n Note9 SLD H disp8 ep reg2 rrr r r 10 0 0 dd d d dd d Note 19 adr ep zero extend disp8 GR reg2 sign extend Load memory adr Half word 1 1 n Note9 SLD HU disp5 ep reg2 Notes 18 20 rr rr r 0 0 0 0 1 1 1 d d d d adr ep zero extend disp5 GR reg2 zero extend Load memory adr Half word 1 1 n Note9 SLD W disp8 ep reg2 rr rr r 1 0 1 0 d d d d d d ...

Page 439: ...ory bit adr bit 3 3 Note3 3 Note3 3 Note3 TST1 reg2 reg1 rrrrr111111RRRRR 0000000011100110 adr GR reg1 Z flag Not Load memory bit adr reg2 3 Note3 3 Note3 3 Note3 XOR reg1 reg2 rrrrr001001RRRRR GR reg2 GR reg2 XOR GR reg1 1 1 1 0 XORI imm16 reg1 reg2 rrrrr110101RRRRR i i i i i i i i i i i i i i i i GR reg2 GR reg1 XOR zero extend imm16 1 1 1 0 ZXB reg1 00000000100RRRRR GR reg1 zero extend GR reg1 ...

Page 440: ...mm9 I I I I Lower 4 bits of imm9 14 In the case of r w the lower 32 bits of the results are not written in the register or w r0 the higher 32 bits of the results are not written in the register 1 15 sp imm specified by bits 19 and 20 of the sub op code 16 ff 00 Load sp in ep 01 Load sign expanded 16 bit immediate data bits 47 to 32 in ep 10 Load 16 bit logically left shifted 16 bit immediate data ...

Page 441: ...r prescaler mode registers 0 to 2 314 BC0 to BC15 167 BCC 117 BCn0 BCn1 n 0 to 7 117 BCT 105 BCYST 57 Block diagram of port 353 Block transfer mode 180 Boundary of memory area 194 Boundary operation conditions 122 BPRM0 to BPRM2 314 BPRn2 to BPRn0 n 0 to 2 314 BRCE0 to BRCE2 314 BRG0 to BRG2 310 BRGC0 to BRGC2 313 BRGn0 to BRGn7 n 0 to 2 313 BS 318 BSC 108 BSn0 BSn1 n 0 to 7 108 BTn0 BTn1 n 0 to 7...

Page 442: ...318 CS0 to CS7 55 CSI0 to CSI3 299 CSIC0 to CSIC3 217 CSIF0 to CSIF3 217 CSIM0 to CSIM3 301 CSMK0 to CSMK3 217 CSOT0 to CSOT3 301 CSPRmn m 0 to 3 n 0 to 2 217 CTBP 72 CTPC 72 CTPSW 72 CTXE0 to CTXE3 301 CVDD 64 CVSS 64 CY 73 D D0 to D7 53 D8 to D15 53 DA0 to DA15 166 DA16 to DA25 165 DAC0n DAC1n n 0 to 3 140 DAD0 DAD1 169 DADC0 to DADC3 168 Data wait control registers 1 2 113 DAW0n DAW1n n 0 to 3 ...

Page 443: ...ternal ROM interface 125 External trigger mode 325 External wait function 114 F FDW 174 FDW0 to FDW7 174 FE0 FE1 291 FECC 72 FEPC 72 FEPSW 72 Flash memory 413 Flash memory programming mode 74 419 Flyby transfer 185 Flyby transfer data wait control register 174 FR2 to FR0 320 Frequency measurement 279 G General purpose registers 71 Global pointer 71 H Halfword access 110 HALT mode 238 High speed pa...

Page 444: ...ddress setting function 190 NMI 51 Noise elimination 208 219 Non maskable interrupt 204 Normal operation mode 74 NP 73 Number of access clocks 107 O OE 57 One time single transfer with DMARQ0 to DMARQ3 196 On page off page judgment 132 Operation in A D trigger mode 329 Operation in external trigger mode 341 Operation in timer trigger mode 332 Operation modes 74 Ordering information 30 OST0 to OST5...

Page 445: ...age ROM access 135 Page ROM configuration register 134 Page ROM controller 130 PB 405 PB0 to PB7 61 405 PC 71 PCS0 370 PCS04 to PCS07 370 PCS1 373 PCS3 380 PCS8 390 PCS10 396 PCS11 400 PCS14 to PCS17 373 PCS35 380 PCS84 PCS85 390 PCS104 to PCS107 396 PCS115 400 PE0 PE1 291 Periods where interrupt is not acknowledged 227 Peripheral I O registers 92 Pin configuration 31 Pin functions 39 Pin input ou...

Page 446: ...e control register 395 Port 11 mode control register 399 Port 12 mode control register 402 Port X mode control register 408 Port 0 mode register 368 Port 1 mode register 371 Port 2 mode register 375 Port 3 mode register 378 Port 4 mode register 381 Port 5 mode register 383 Port 6 mode register 385 Port 8 mode register 388 Port 9 mode register 392 Port 10 mode register 394 Port 11 mode register 398...

Page 447: ...AD1 168 SAT 73 Scan mode 328 SCK0 SCK1 51 SCK2 52 SCK3 59 SCLS00 SCLS01 SCLS10 SCLS11 289 Securing oscillation stabilization time 244 SEIC0 SEIC1 217 SEIF0 SEIF1 217 Select mode 325 Self refresh functions 158 SEMK0 SEMK1 217 SEPR0n SEPR1n n 0 to 2 217 Serial I O shift registers 0 to 3 303 Serial interface function 283 SI0 SI1 51 SI2 52 SI3 59 Single chip modes 0 1 74 Single step transfer mode 180 ...

Page 448: ... 251 Timers 40 41 253 Timer counter function 247 TM0 TM1 169 TM10 to TM15 251 TM40 TM41 253 TMC10 to TMC15 257 TMC40 TMC41 259 TO100 TO101 49 TO110 TO111 50 TO120 TO121 58 TO130 TO131 52 TO140 TO141 59 TO150 TO151 60 TOC10 to TOC15 260 TOVS 261 Transfer mode 179 Transfer objects 189 Transfer of misalign data 194 Transfer types 181 Transmission completion interrupt 294 Transmit shift registers 0 0L...

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Summary of Contents for V850E/MS1 UPD703100

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NEC V850E/MS1 UPD703100, User Manual

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Summary of Contents for V850E/MS1 UPD703100

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