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13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.3 Communication using the multiple CPU high speed transmission area and auto refresh
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(c) Memory structure of the multiple CPU high speed transmission area
The following explains memory structure of the multiple CPU high speed
transmission area in the CPU shared memory.(
(d) Settings required for auto refresh
To perform auto refresh, the points of data to be sent from each CPU module must
be set in "Multiple CPU high speed transmission area setting" in <<Multiple CPU
settings>> of C Controller setting utility.
Remark
For C Controller setting utility, refer to the following.
C Controller Module User's Manual (Utility Operation, Programming)
Figure 13.18 Memory structure of the multiple CPU high speed transmission area
Table 13.12 Multiple CPU high speed transmission area
No.
Name
Description
Size
Setting
range
Setting
unit
1)
Multiple CPU high speed
transmission area
• The area for data communications between CPU modules in
a multiple CPU system.
• An area of up to 14K words is divided into sub-areas for
respective CPU modules in a multiple CPU system.
0 to 14K
words
1K word
2)
CPU No.n send area
• The area where send data of each CPU module are stored.
• Data stored in the host CPU's send area are sent to another
CPU.
• Data received from another CPU are stored in the send area
for another CPU.
0 to 14K
words
1K word
3)
User setting area
• The area for communicating data with other CPUs using
cyclic transmission area devices.
• Accesses are performed with the user program that uses
cyclic transmission area devices.
0 to 14K
words
2 words
4)
Auto refresh area
• The area for communicating device data with other CPUs
using auto refresh.
0 to 14K
words
2 words
1) Multiple CPU
high speed
transmission area
2) CPU No.1 send area
3) User setting area
2) CPU No.2 send area
2) CPU No.3 send area
2) CPU No.4 send area
4) Auto refresh area
Summary of Contents for Q06CCPU-V
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