13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13
- 13
9
DE
V
ICE DE
S
CRIPT
IO
N
10
MU
LT
IPL
E
CP
U SY
S
T
EM
O
V
ER
VI
E
W
11
MUL
T
IP
L
E
CP
U
S
Y
S
TE
M
CONFIGURA
TION
12
CONCE
PT
OF MU
LT
IPL
E
CP
U SY
S
T
EM
13
COMMUN
ICA
TIO
N
S
BE
TWE
E
N
CP
U
MODUL
ES
14
P
A
RAM
E
TE
RS
A
DDE
D
F
O
R MU
LT
IP
LE
C
P
U
S
YSTE
M
S
15
ST
A
R
TIN
G A
M
U
LT
IPLE
CP
U
SYS
TEM
16
TR
O
U
B
L
E
S
HOOTING
POINT
The CPU shared memory is accessible only when the number of CPUs is set to 2
or more in <<Multiple CPU settings>> of C Controller setting utility.
If the CPU shared memory is accessed without setting two or more CPU modules,
CPU No. error (return value: -28662) is detected.
Remark
For the bus interface functions, refer to the following.
C Controller Module User's Manual (Utility Operation, Programming)
Summary of Contents for Q06CCPU-V
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