LTC3882-1
71
Rev A
PMBUS_REVISION
The PMBUS_REVISION command returns the revision of the PMBus Specification that the device supports. The
LTC3882-1 is compliant with PMBus Version 1.2, both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
The CAPABILITY command reports some key LTC3882-1 features to the PMBus host device.
The LTC3882-1 supports packet error checking, 400kHz bus speeds and has an
ALERT
output.
This read-only command has one data byte.
GENERAL DEVICE CONFIGURATION
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
PMBUS_REVISION
0x98 Supported PMBus version.
R Byte
Y
Reg
0x22
V1.2
CAPABILITY
0x19 Summary of supported optional PMBus
features.
R Byte
N
Reg
0xB0
MFR_CONFIG_ALL_LTC3882-1
0xD1 LTC3882-1 device-level configuration.
R/W Byte
N
Reg
l
0x01
PMBus COMMAND DETAILS
(Addressing and Write Protect)
MFR_ADDRESS
The MFR_ADDRESS command sets the seven bits of the PMBus device address for this unit (right justified).
Setting this command to a value of 0x80 disables device-level addressing. The GLOBAL device addresses 0x5A and
0x5B cannot be disabled. The LTC3882-1 always responds at these addresses. Even if bit 6 of MFR_CONFIG_ALL_
LTC3882-1 is set to ignore the device resistor configuration pins, any valid address, or portion of an address, specified
with external resistors on ASEL0 or ASEL1 is applied. If both of these pins are open, the device address is determined
for additional details.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command sets a direct 7-bit PMBus address (right justified) for the active channel(s) as
determined by the PAGE command. This address should be common to all channels attached to a single power supply
rail. Setting this command to a value of 0x80 disables rail device addressing for the selected channel. Only command
writes should be made to the rail address. If a read is performed from this address, a CML fault may result.
This command has one data byte.
