LTC3882-1
42
Rev A
For more information
APPLICATIONS INFORMATION
Efficiency Considerations
Normally, one of the primary goals of any LTC3882-1 ap-
plication will be to obtain the highest practical conversion
efficiency. The efficiency of a switching regulator is equal
to the output power divided by the input power. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and to ascertain which change would
produce the most improvement. Balancing or limiting these
individual losses plays a dominant role in the component
selection process outlined over the next few sections.
Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, et al, are the individual losses as a percent-
age of input power: 100 • P
L
n
/P
IN
.
Although all dissipative elements in the system produce
losses, four main sources usually account for most of
the losses in LTC3882-1 applications: IC supply current,
I
2
R losses, topside power MOSFET transition losses and
total gate drive current.
1. The LTC3882-1 IC supply current is a DC value given
in the Electrical Characteristics table. The absolute loss
created by the IC itself is approximately this current
times the V
CC
supply voltage. IC supply current typically
results in a small loss (<0.1%).
2. I
2
R losses occur mainly in the DC resistances of the
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
of the cycle, its on-resistance is effectively multiplied by
the percentage of the cycle it is on. Therefore the bot-
tom MOSFET should have a much lower on-resistance
R
DS(ON)
than the top MOSFET in high step-down ratio
applications. It is crucial that careful attention is paid
to the layout of the power path on the PCB to minimize
its resistance. In a 2-phase 1.2V system, 1mΩ of PCB
resistance at the output costs 5% in efficiency with the
output running at 60A.
3. Transition losses apply only to the topside MOSFET and
become significant when operating at high input voltages
(typically above 12V). This loss can be minimized by
choosing a driver with very low drive resistance and a
MOSFET with low gate charge Q
G
, gate resistance R
G
and Miller capacitance C
MILLER
. Absolute transition loss
can be estimated by:
P
TRANS
= (1.7) • V
IN
2
• I
OUT
• C
MILLER
• f
PWM
4. Gate drive current is equal to the sum of the top and bot-
tom MOSFET gate charges multiplied by the frequency of
operation. These charges are based on the gate voltage
applied by the FET driver and can be determined from
manufacturer curves like the one shown in Figure 21
Many driver ICs employ asymmetrical gate voltages for
top and bottom FETs.
Other sources of loss include body or Schottky diode
conduction during the driver dependent non-overlap time
and inductor core losses. These latter categories generally
account for less than 2% total additional loss.
PWM Frequency and Inductor Selection
The selection of the PWM switching frequency is a trade-off
between efficiency, transient response and component size.
High frequency operation reduces the size of the inductor
and output capacitor as well as increasing the maximum
practical control loop bandwidth. However, efficiency is
generally lower due to increased transition and switch-
ing losses. The inductor value is related to the switching
frequency f
PWM
and step-down ratio. It should be selected
to meet choke ripple current requirements. The inductor
value can be calculated using the following equation:
L
=
V
OUT
f
PWM
•
Δ
I
L
⎛
⎝⎜
⎞
⎠⎟
• 1–
V
OUT
V
IN
⎛
⎝⎜
⎞
⎠⎟
Allowing a larger value of choke ripple current (∆I
L
) leads
to smaller L, but results in greater core loss and higher
output voltage ripple for a given output capacitance and/
or ESR. A reasonable starting point for setting the ripple
current is 30% of the maximum output current.
The inductor saturation current rating needs to be higher
than the peak inductor current during transient conditions.
If I
OUT
is the maximum rated load current, then the maxi-
mum transient current I
MAX
would normally be chosen to
be some factor greater than I
OUT
(e.g., 1.6 • I
OUT
).
