LTC3882-1
22
Rev A
For more information
OPERATION
can also be set from EEPROM or external configuration
resistors as outlined in Table 10. Phase designates the
relationship between the falling edge of SYNC and the
internal clock edge that resets the PWM latch. That reset
turns off the top power switch, producing a PWM falling
edge. Additional small propagation delays to the PWM
control pins will apply.
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC3882-1 ICs can be synchronized to realize a
PolyPhase array. In this case the phases should be sepa-
rated by 360/n degrees, where n is the number of phases
driving the output voltage rail.
PolyPhase Load Sharing
Multiple LTC3882-1 ICs can be combined to provide a bal-
anced load-share solution by configuring the necessary
pins. The SHARE_CLK and SYNC pins of all load-sharing
channels should be bussed together. Connecting the
SYNC pins synchronizes the PWM controllers with each
other. Bussing the SHARE_CLK pins together allows the
phases to start synchronously. Refer to the discussion in
the previous Power-Up and Initialization section. The last
device to see all start-up conditions satisfied controls the
initiation of power sequencing for all phases.
Due to the low output impedance of the LTC3882-1 error
amplifiers, PolyPhase applications should use the error
amplifier of only one phase as the master. The FB pins of
each slave channel must be wired to V
DD33
, and the COMP
pins of each slave phase must be connected to the master
error amplifier COMP output. This disables the slave error
amplifiers and provides a single point of voltage control
and loop stabilization for the PolyPhase output rail.
For PolyPhase load sharing the LTC3882-1 also incorporates
an auxiliary current sharing loop. Referring back to Figure 1,
the instantaneous current of each slave phase is sensed
by current amplifier CA and compared to the I
AVG
pin. The
I
AVG
and I
AVG_GND
pins of each phase are wired together,
and a small capacitor (50pF to 200pF) between I
AVG
and
I
AVG_GND
stores a voltage corresponding to the average
master phase output current. The difference in this aver-
age and the instantaneous phase current is integrated.
The output of integrator S of each slave phase is then
proportionally summed with the master error amplifier
COMP output to adjust the duty cycle and balance the
current contribution of that phase. Additional hardware
configuration and digital programming requirements apply
in PolyPhase systems. Refer to the Applications Informa-
tion section for complete details on building PolyPhase
rails with the LTC3882-1.
Active Voltage Positioning
Load slope is programmable in the LTC3882-1 via the
MFR_VOUT_AVP PMBus command. The inductor cur-
rent measured at the I
SENSE
pins is converted to a voltage
which is then subtracted from the voltage reference at the
positive input of the error amplifier. The final load slope
is defined by the inductor current sense element and the
bits set in the MFR_VOUT_AVP PMBus command. Setting
MFR_VOUT_AVP to a value greater than 0.0% automatically
disables output servo mode for that channel.
Input Supply Monitoring
The input supply voltage is sensed by the LTC3882-1 at the
VINSNS pin. Undervoltage, overvoltage, valid on and off
levels can be programmed for V
IN
. Refer to the following
PMBus Command Details section for more information on
programming the input supply thresholds. In addition, the
telemetry ADC monitors the VINSNS voltage relative to
GND. Conversion results are returned by the READ_VIN
PMBus command.
Output Voltage Sensing and Monitoring
Both PWM channels allow remote, differential sensing of the
load voltage with V
SENSE
pins. The channel 1 output sense
pin V
SENSE1
–
is internally shorted to GND (the exposed
pad). The telemetry ADC is fully differential and makes its
measurements of the output voltages of channels 0 and 1
at V
SENSE0
±
and V
SENSE1
±
, respectively. Conversion results
are returned by the READ_VOUT PMBus command.
Output Current Sensing and Monitoring
Both channels allow differential sensing of the inductor
current using either the inductor DCR or a resistor in series
with the inductor across the I
SENSE
pins. When the I
SENSE
pins for a channel are multiplexed to the differential inputs
