LTC3882-1
14
Rev A
For more information
PIN FUNCTIONS
PHAS_CFG (Pin 21):
Phase Configuration Pin. Connect
an optional 1% resistor divider between V
DD25
and GND
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail.
V
DD25
(Pin 22):
Internal 2.5V Regulator Output. Bypass
this pin to GND with a low ESR 1µF capacitor. Do not load
this pin with external current beyond that required for local
LTC3882-1 configuration pins, if any.
SHARE_CLK (Pin 23):
Share Clock Open-Drain Output
(bussed). Share Clock, nominally 100kHz, is used to
sequence multiple rails in a power system utilizing more
than one LTC PSM controller. A pull-up resistor is required
in the application. Minimize the capacitance on this line to
ensure the time constant is fast enough for the application.
Operating voltage range is GND to V
DD33
.
V
DD33
(Pin 24):
Internal 3.3V Regulator Output. Bypass this
pin to GND with a low ESR 2.2µF capacitor. The LTC3882-1
may also be powered from an external 3.3V rail attached
to this pin, if also shorted to V
CC
. Do not overload this pin
with external system current. Local pull-up resistors for
the LTC3882-1 itself may be powered from V
DD33
. Refer
to the Applications Information section for more detail.
V
CC
(Pin 25):
3.3V Regulator Input. Bypass this pin to
GND with a capacitor (0.1µF to 1µF ceramic) in close
proximity to the IC.
V
SENSE0
–/
V
SENSE1
–
(Pin 35/Pin 34):
Negative Output
Voltage Sense Inputs. These pins must still be properly
connected on slave channels for accurate output current
telemetry.
V
SENSE0
+
/V
SENSE1
+
(Pin 36/Pin 33):
Positive Output Voltage
Sense Inputs. These pins must still be properly connected
on slave channels for accurate output current telemetry.
I
SENSE0
–
/I
SENSE1
–
(Pin 37/Pin 32):
Current Sense Ampli-
fier Inputs. The (–) inputs to the amplifiers are normally
connected to the low side of a DCR sensing network or
output current sense resistor for each phase.
I
SENSE0
+
/I
SENSE1
+
(Pin 38/Pin 31):
Current Sense Ampli-
fier Inputs. The (+) inputs are normally connected to the
high side of an output current sense resistor or the R-C
midpoint of a parallel DCR sense circuit.
I
AVG0
/I
AVG1
(Pin 39/Pin 30):
Average Current Control Pins.
A capacitor connected between these pins and I
AVG_GND
stores a voltage proportional to the average output current
of the master channel. PolyPhase control is then imple-
mented in part by connecting all slave I
AVG
pins together
to the master I
AVG
output. This pin should be left open
on channels that control single-phase outputs. Operating
voltage range is GND to 2.1V.
FB0/FB1 (Pin 40/Pin 29):
Error Amplifier Inverting Inputs.
These pins provide an internally scaled version of the
output voltage for use in loop compensation. Refer to the
Applications Information section for additional details on
compensating the output voltage control loop with external
components.
GND (Exposed Pad Pin 41):
Ground. All small-signal and
compensation components should connect to this pad.
The exposed pad must be soldered to a suitable PCB copper
ground plane for proper electrical operation and to obtain
the specified package thermal resistance.
