LTC3882-1
28
Rev A
For more information
OPERATION
• The LTC3882-1 Successfully Transmits Its Address
During a PMBus Alert Response Address (ARA)
• IC Supply Power Is Cycled
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTC3882-1 from asserting
ALERT
for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if
ALERT
is masked for all bits
in Channel 0 STATUS_VOUT, then
ALERT
is effectively
masked for the VOUT bit in STATUS_WORD for PAGE 0.
The BUSY bit in STATUS_BYTE also asserts
ALERT
low
and cannot be masked. This bit can be set as a result of
interaction between internal operation and PMBus com-
munication. This fault occurs when a command is received
that cannot be safely executed with one or both channels
enabled. As discussed in Application Information, BUSY
faults can be avoided by polling MFR_COMMON before
executing some commands.
Status information contained in MFR_COMMON and
MFR_PADS_LTC3882-1 can be used to clarify the con-
tents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the
ALERT
pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
FAULT
Pin I/O
The LTC3882-1 can map various fault indicators to their
respective
FAULT
pin using the MFR_FAULT_PROPA-
GATE_LTC3882-1 command.
Channel-to-channel fault dependencies and communica-
tion can be created by connecting
FAULT
pins together. In
the event of an internal fault, one or more of the channels
is configured to pull the bussed
FAULT
pins low. All chan-
nels are then configured to shut down when the bussed
FAULT
pins are pulled low (MFR_FAULT_RESPONSE set
to 0xc0). If latch off is the programmed response on the
faulted channel, the
FAULT
pin remains low until one of
the following occurs:
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RE-
SET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
• IC Supply Power Is Cycled
For autonomous group retry, the faulted channel is con-
figured to release the
FAULT
pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence.
As noted above,
FAULT
pins may be configured as inputs
to detect faults external to the controller that require an
immediate response. External faults propagated into the
chip using
FAULT
pins are not deglitched.
Refer to the MFR_FAULT_PROPAGATE command for ad-
ditional details.
Fault Logging
The LTC3882-1 features a fault log, providing telemetry
recording capability. During normal operation log data is
continuously updated in internal RAM. When a fault occurs
that disables either PWM controller, recording to internal
memory is halted, the fault log information is made avail-
able from RAM via the MFR_FAULT_LOG command, and
the contents of the RAM log are copied into EEPROM.
Refer to the Fault Log Operation section for more detail.
EEPROM fault logging is allowed above a die temperature
of 85°C, but 10 years of retention is not guaranteed. When
die temperature exceeds 130°C EEPROM fault logging is
delayed until the temperature drops below 125°C. Faults
generating a log should be fully cleared before the log is
erased to prevent generation of spurious fault logs. Faults
propagated into the IC through
FAULT
n
pins do not trigger
a fault logging event.
When the LTC3882-1 powers up it checks the EEPROM
for a valid fault log. If one is found the Valid Fault Log bit
in the STATUS_MFR_SPECIFIC PMBus command is set.
Additional fault logging will be disabled until the LTC3882-1
receives a CLEAR_FAULTS command. If the Memory Fault
Detected bit is also set in STATUS_CML, then the stored
fault log is partial. Data in one or more event records may
be incomplete or incorrect and MFR_FAULT_LOG_CLEAR
should also be commanded after all faults are cleared in
order to fully enable additional logging functions.
