LTC3882-1
68
Rev A
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The frequency and phase are also set by EEPROM values.
Assume that solution footprint or vertical clearance is an
issue, so operating frequency will need to be increased
in an effort to minimize inductor value (size). This choice
could also result from the need to have above average
transient performance, although efficiency may be re-
duced slightly. FREQUENCY_SWITCH is set to 1.0MHz.
As a 2-phase system, MFR_PWM_CONFIG_LTC3882-1
is programmed to 0x14 to put Channel 0 phase at 0° and
Channel 1 phase at 180°. This produces the lowest input
ripple possible with this configuration and allows this
output to synchronize with other rails via SHARE_CLK.
The design will plan on a nominal output ripple of 70% of
I
OUT
to minimize the magnetics volume, and the inductance
value is chosen based on this assumption. Each channel
supplies an average 20A to the output at full load, result-
ing in a ripple of 14A
P-P
. A 200nH inductor per phase
would create this peak-to-peak ripple at 1.0MHz. A Pulse
PA0513.22LT 210nH inductor with a DCR of 0.32mΩ
typical is selected. Setting IOUT_FAULT_LIMIT to 35A per
phase leaves plenty of headroom for transient conditions
while still adequately protecting against the rated inductor
saturation current of 45A at temperature.
For top and bottom power FETs, the 40V rated Infineon
BSC050N04LSG and BSC010N04LS are chosen, respec-
tively. These afford both low R
DS(ON)
and low gate charge
Q
G
. Two of each of these could be paralleled to achieve
improved efficiency at full load, if desired.
The LTC4449 gate driver is chosen for its fast response
(13ns), suitable gate drive, V
IN
capability (38V) and the
ease with which it can be interfaced to the LTC3882-1. Basic
three-state control, CCM operation, fast boost refresh, low
V
OUT
range and digital output voltage servo are selected
by programming MFR_PWM_MODE_LTC3882-1 to 0xC0
for both channels.
For input filtering, a 47μF SUNCON capacitor and four
22μF ceramic capacitors are selected to provide accept-
able AC impedance against the designed converter ripple
current. Four 470μF 9mΩ POSCAPs and two 100μF
ceramic capacitors are chosen for the output to maintain
supply regulation during severe transient conditions and
to minimize output voltage ripple.
A loop crossover frequency of 100kHz provides good
transient performance while still being well below the
switching frequency of the converter. The values of R29,
R30 and C25 to C27 were determined to produce a nomi-
nal system phase margin of about 65° at this bandwidth.
For the DCR sense filter network, R = 3.09k and C = 220nF
are chosen to match the L/DCR time constant of the induc-
tor. PolyPhase connections (I
AVG
, et al) are shown in the
schematic to ensure good output current sharing between
the two power stages.
External temperature sense will employ an accurate ∆V
BE
method, and Q1 and Q2 serve to sense the temperature of
L1 and L2, respectively. These components will be located
immediately adjacent to their chokes and the 10nF filter
capacitors placed with the BJTs.
Resistor configuration is used on the ASEL
n
pins to pro-
gram PMBus address (MFR_ADDRESS) to 0x4C. Each
LTC3882-1 must be configured for a unique address.
Using both ASEL
n
pins to accomplish this programming
is recommended for simpliest in-system programming.
Check the selected address to avoid collision with global
addresses other any other specific devices. Identical
MFR_RAIL_ADDRESS can be set in EEPROM for both
channels to allow single-command control of common
rail parameters such as IOUT_OC_FAULT_LIMIT. The
LTC3882-1 also responds to 7-bit global addresses 0x5A
and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS
should not be set to either of these values.
PMBus connection (three signals), as well as shared
RUN control and fault propagation (
FAULT
) are provided.
SYNC can be used to synchronize other PWMs to this
rail if required.
Pull-ups are provided on all these shared open-drain signals
assuming a maximum 100pF line load and PMBus rate of
100kHz. These pins should not be left floating. Termina-
tion to 3.3V ensures the absolute maximum ratings for
the pins are not exceeded. All other operating parameters
such as soft start/stop and desired faults responses are
programmed via PMBus command values stored in internal
LTC3882-1 EEPROM.
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