LTC3882-1
96
Rev A
For more information
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The device also:
• Sets the IOUT_OC Bit in the STATUS_BYTE
• Sets the IOUT Bit in the STATUS_WORD
• Sets the I
OUT
Overcurrent Fault Bit in the STATUS_IOUT Command
• Notifies the Host by Asserting
ALERT
Output overcurrent faults are ignored during TON_RISE and TOFF_FALL output sequencing.
Data Byte Contents for IOUT_OC_FAULT_RESPONSE:
BITS
DESCRIPTION
VALUE
MEANING
[7:6]
For all values of bits [7:6], the LTC3882-1:
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting
ALERT
, unless masked.
The fault, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The corresponding STATUS_IOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
0x
The LTC3882-1 continues to operate indefinitely with the
normal hardware response described in the Operation
section.
10
The LTC3882-1 continues operating with the normal
hardware response for the delay time specified by bits
[2:0]. If the fault is continuously present for the entire delay,
the unit then disables the output and does not attempt to
restart.
11
The LTC3882-1 shuts down (disables the output) and
responds according to the retry setting in bits [5:3].
[5:3]
Retry setting.
000-110
The LTC3882-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or bias power is cycled.
111
The LTC3882-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY.
This response persists until the unit is commanded off,
bias power is removed, or another fault response forces
shutdown without retry.
[2:0]
Delay time.
xxx
Response delay time in 16ms increments. This delay time
determines how long the fault may have to persist before
the controller is disabled, depending on bits [7:6]. These
bits always return zero if bits [7:6] are not set to 0x2.
Programming an unsupported IOUT_OC_FAULT_RESPONSE value will generate a CML fault and the command will
be ignored.
This command has one data byte.
PMBus COMMAND DETAILS
(Fault Response and Communication)
