LTC3882-1
75
Rev A
MFR_PWM_CONFIG_LTC3882-1
The MFR_PWM_CONFIG_LTC3882-1 command controls PWM-related clocking for the LTC3882-1. Both PWM chan-
nels must be turned off by the RUN
n
pins, OPERATION command, or their combination, to process this command. If
this command is sent while either PWM controller is operating, the LTC3882-1 will NACK the command byte, ignore
the command and its data, and assert a BUSY fault.
Supported Values:
BIT
MEANING
7
(Reserved, must write as 0).
6
(Reserved, must write as 0).
5
(Reserved).
4
SHARE_CLK configuration:
0: SHARE_CLK continuously enabled once VINSNS ≥ VIN_ON after initialization.
1: SHARE_CLK always forced low if VINSNS ≤ VIN_OFF, then held low until VINSNS ≥ VIN_ON.
3
(Reserved).
2:0
Value
Phase
Maximum Duty
Cycle
Channel 0
Channel 1
111b
135°
315°
87.5%
110b
90°
270°
101b
45°
225°
100b
0°
180°
011b
120°
300°
83.3%
010b
60°
240°
001b
0°
180°
000b
0°
120°
Phase is expressed from the falling edge of SYNC to the falling edge of PWM.
This command has one data byte.
PMBus COMMAND DETAILS
(PWM Configuration)
