LTC3882-1
45
Rev A
APPLICATIONS INFORMATION
capacitance than is required to keep capacitance-based
droop under control.
The input capacitance voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
occurs as I
2
R dissipation in the capacitor itself. The input
capacitor RMS current and its impact on any preceding
input network is reduced by PolyPhase architecture. It can
be shown that the worst case RMS current occurs when
only one controller is operating. The controller with the
highest (V
OUT
)(I
OUT
) product should be used to determine
the maximum RMS current requirement. Increasing the
output current drawn from the other out-of-phase control-
ler will decrease the input RMS ripple current from this
maximum value. Two channel out-of-phase operation
typically reduces the input capacitor RMS ripple current
by a factor of 30% to 70%.
In continuous inductor conduction mode, the source cur-
rent of the top power MOSFET is approximately a square
wave of duty cycle V
OUT
/V
IN
. The maximum RMS capacitor
current in this case is given by:
I
RMS
≈
I
OUT(MAX)
V
OUT
V
IN
– V
OUT
(
)
V
IN
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief.
Note that manufacturer ripple current ratings for capacitors
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
Ceramic, tantalum, semiconductor electrolyte (OS-CON),
hybrid conductive polymer (SUNCON) and switcher-rated
electrolytic capacitors can be used as input capacitors, but
each has drawbacks. Ceramics have high voltage coeffi-
cients of capacitance and may have audible piezoelectric
effects; tantalums need to be surge-rated; OS-CONs suffer
from higher inductance, larger case size and limited surface
mount applicability; and electrolytic capacitors have higher
ESR and can dry out. Sanyo OS-CON SVP(D) series, Sanyo
POSCAP TQC series, or Panasonic EE-FT series aluminum
electrolytic capacitors can be used in parallel with a couple
of high performance ceramic capacitors as an effective
means of achieving low ESR and high bulk capacitance.
In addition to PWM bulk input capacitance, a small (0.01μF
to 1μF) bypass capacitor between the chip VINSNS pin
and ground, placed close to the LTC3882-1, is also sug-
gested. A small resistor placed between the bulk C
IN
and
the VINSNS pin provides further isolation between the two
channels. However, if the time constant of any such R-C
network on the VINSNS pin exceeds 30ns, dynamic line
transient response can be adversely affected.
C
OUT
Selection
The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The output ripple ∆V
OUT
is approximately bounded by:
Δ
V
OUT
≤ Δ
I
L
ESR
+
1
8 • f
PWM
•C
OUT
⎛
⎝⎜
⎞
⎠⎟
where ∆I
L
is the inductor ripple current.
Δ
I
L
=
V
OUT
L • f
PWM
1–
V
OUT
V
IN
⎛
⎝⎜
⎞
⎠⎟
Since ∆I
L
increases with input voltage, the output ripple
voltage is highest at maximum input voltage. Typically
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Manufacturers such as Sanyo, Panasonic and Cornell Du-
bilier should be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has a good (ESR)(size)
product. An additional ceramic capacitor in parallel with
polarized capacitors is recommended to offset the effect
of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
