LTC3882-1
19
Rev A
VC discriminates its positive input against an internally
generated PWM voltage ramp. The positive input is a com-
posite control based on COMP voltage with line feedforward
compensation, and current sharing if the channel controls
a slave phase. When the ramp falls below this voltage the
comparator trips and sets the PWM latch.
If load current increases, V
SENSE
+
and FB will droop
slightly with respect to the 12-bit DAC output. This causes
the COMP voltage to increase until the average inductor
current matches the new load current and the desired
output voltage is restored. Programmable comparators
I
LIM
and I
REV
monitor peak instantaneous forward and
reverse inductor current for pulse-by-pulse protection.
The top power MOSFET is immediately commanded off if
the programmed positive limit is reached, and the bottom
MOSFET is immediately commanded off if the negative
limit is reached. Repeated peak overcurrent events cause
an overcurrent fault to be set.
When the top MOSFET is commanded off, the bottom
MOSFET is normally commanded on. In continuous con-
duction mode (CCM) the bottom MOSFET stays on until
comparator VC turns the top MOSFET back on. Otherwise
in discontinuous conduction mode (DCM, also known as
diode emulation) the bottom MOSFET is commanded off
if the I
REV
comparator detects that the inductor current
has decayed to approximately 0A. In any case the next
PWM cycle starts when the clock for that channel again
clears the RS latch.
Power-Up and Initialization
The LTC3882-1 is designed to provide stand-alone supply
sequencing with controlled turn-on and turn-off functions.
It operates from a single IC input supply of 3V to 13.2V
while two on-chip linear regulators generate internal
2.5V and 3.3V. If V
CC
is below 4.5V, the V
CC
and V
DD33
pins must be shorted together and limited to a maximum
operating voltage of 3.6V. Controller configuration is
reset by the internal UVLO threshold, where V
DD33
must
be at or above 3V and the internal 2.5V supply must be
within about 20% of its regulated value. At that point the
internal microcontroller begins initialization. A PMBus
RESTORE_USER_ALL or MFR_RESET command forces
this same initialization.
The LTC3882-1 features an internal RAM built-in self-test
(BIST) that runs during initialization. Should RAM BIST
fail, the following steps are taken.
• Device responds only at device address 0x7C and global
addresses 0x5A and 0x5B
• A persistent Memory Fault Detected is indicated by
STATUS_CML
• Internal EEPROM is not accessed
• RUN
n
and SHARE_CLK are driven low continuously
Normal operation can be restored if the RAM BIST sub-
sequently passes, for instance as the result of another
MFR_RESET command issued to address 0x7C.
During initialization all PWM outputs are disabled. The
RUN
n
pins and SHARE_CLK are held low and
FAULT
n
pins are high impedance. External configuration resistors
are identified and the contents of the onboard EEPROM
are read into the controller command memory space. The
LTC3882-1 can determine key operating parameters from
external configuration resistors according to application
Table 8 through Table 11. See the following Resistor
Configuration Pins section for more detail. The resistor
configuration pins only determine some of the preset
values of the controller. The remaining values, retrieved
from internal EEPROM, are programmed at the factory or
with PMBus commands.
If the configuration resistor pins are all open, the LTC3882-1
will use only EEPROM contents to determine all operating
parameters. If Ignore Resistor Configuration Pins is set (bit
6 of MFR_CONFIG_ALL_LTC3882-1), the LTC3882-1 will
use only its EEPROM contents to determine all operating
parameters except device address. Unless both ASEL pins
are completely open, the LTC3882-1 will always determine
some portion of its device address from the resistors on
these pins. See Serial Bus Addressing later in this section.
The internal microcontroller typically requires 35ms to
complete initialization from VDD33 ≥ 3V. At that point, an
internal comparator monitors VINSNS, which must exceed
the VIN_ON threshold before output power sequencing
can begin (SHARE_CLK released, ready for TON_DELAY).
Accurate readback telemetry can then require an additional
90ms for initial round-robin A/D conversions.
OPERATION
