LTC3882-1
63
Rev A
APPLICATIONS INFORMATION
If an external source supplies V
DD33
directly, the following
formula may be used to estimate the maximum average
power dissipation P
D
(in watts) of the LTC3882-1
P
D
= V
DD33
(0.024 + f
PWM
• 1.6e-5 + I
RC25
)
The maximum junction temperature of the LTC3882-1 in
°C may then be found from the following equation
T
J
= T
A
+ 33 • P
D
with ambient temperature T
A
expressed in °C
Derating EEPROM Retention at Temperature
EEPROM read operations between 85°C and 125°C will not
affect data storage. But retention will be degraded if the
EEPROM is written above 85°C or stored above 125°C. If
an occasional fault log is generated above 85°C, the slight
reduction in data retention in the EEPROM fault log area
will not affect the use of the function or other EEPROM
storage. See the Operation section for other high tem-
perature EEPROM functional details. Degradation in data
can be approximated by calculating the dimensionless
acceleration factor using the following equation.
AF
=
e
Ea
k
⎛
⎝⎜
⎞
⎠⎟
•
1
T
USE
+
273
−
1
T
STRESS
+
273
⎛
⎝⎜
⎞
⎠⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
Where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.617 • 10
–5
eV/°K
T
USE
= is the specified junction temperature
T
STRESS
= actual junction temperature in °C
As an example, if the device is stored at 130°C for 10 hours,
T
STRESS
= 130°C, and
AF
=
e
1.4
8.617•10
–5
⎛
⎝⎜
⎞
⎠⎟
•
1
398
−
1
403
⎛
⎝⎜
⎞
⎠⎟
⎡
⎣
⎢
⎤
⎦
⎥
=
1.66
indicating the effect is the same as operating the device at
125°C for 10 • 1.66 = 16.6 hours, resulting in a retention
derating of 6.6 hours.
Configuring Open-Drain Pins
The LTC3882-1 has the following open-drain pins:
3.3V Pins
1. PGOOD
n
2.
FAULT
n
2. SYNC
3. SHARE_CLK
5V-Capable Pins
(These pins operate correctly when pulled to 3.3V.)
1. RUN
n
2.
ALERT
3. SCL
4. SDA
All of the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low-state threshold on
these pins provides ample noise margin exists with 3mA
of current. For 3.3V pins, 3mA of current is produced by
a 1.1k pull-up resistor. Unless there are transient speed
issues associated with the RC time constant of the net, a
10k resistor or larger is generally recommended.
The pull-up resistor for PGOOD should be terminated to
the LTC3882-1 V
DD33
pin or a separate bias supply under
3.6V that is up before the LTC3882-1 is enabled. Otherwise,
power-not-good may be falsely indicated after the PWM
outputs are running.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 250ns when driven by
the LTC3882-1. If the internal oscillator is set for 500kHz
and the load is 100pF with a 1/3 rise time required, the
resistor calculation is as follows:
R
PULLUP
=
2µs – 250ns
3 • 100pF
=
5.83k
The closest 1% resistor is 5.76k.
If timing errors are occurring or if the SYNC amplitude
is not as large as required, monitor the waveform and
determine if the RC time constant is too long for the
