LTC3882-1
64
Rev A
For more information
APPLICATIONS INFORMATION
application. If possible reduce the parasitic capacitance.
Otherwise reduce the pull-up resistor sufficiently to assure
proper operation.
The SHARE_CLK output has a nominal period of 10μs
and is pulled low for about 1μs. If the system load on this
shared line is 100pF, the resistor calculation for this line
with a 1/3 rise time is:
R
PULLUP
=
9µs
3 • 100pF
=
30k
The closest 1% resistor is 30.1k.
For high speed signals such as SDA, SCL and SYNC, a
lower value resistor may be required. The RC time constant
should be set to 1/3 to 1/5 the required rise time to avoid
timing issues. For a 100pF load and a 400kHz PMBus com-
munication rate, the resistor pull-up on the SDA and SCL
pins with the time constant set to 1/3 the rise time equals
R
PULLUP
=
t
RISE
3 • 100pF
=
1k
The closest 1% resistor value is 1k.
Be careful to minimize parasitic capacitance on the SDA
and SCL lines to avoid communication problems. To
estimate the loading capacitance, monitor the signal in
question and measure how long it takes for the desired
signal to reach approximately 63% of the output value.
This is one time constant.
PMBus Communication and Command Processing
The LTC3882-1 has a one deep buffer to hold the last data
written for each supported command prior to processing,
as shown in Figure 45. Two distinct parallel sections of
the LTC3882-1 manage command buffering and command
processing to ensure the last data written to any command
is never lost. When the part receives a new command
from the bus, command data buffering copies the data
into the write command data buffer and indicates to the
internal processor that data for that command should be
handled. The internal processor runs in parallel and per-
forms the sometimes slower task of fetching, converting
(to internal format) and executing commands so marked
for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long
relative to PMBus timing. If the part is busy processing
a command, and a new command(s) arrives, execution
may be delayed or processed in a different order than
received. The part indicates when internal calculations
are in process with bit 5 of MFR_COMMON (LTC3882-1
Calculations Not Pending). When the internal proces-
sor is busy calculating, bit 5 is cleared. When this bit is
set, the part is ready for another command. An example
polling loop is provided in Figure 46, which ensures that
commands are processed in order while simplifying error
handling routines. MFR_COMMON always returns valid
data at PMBus speeds between 10kHz and 400kHz.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification V1.2, Part II, Section 10.8.7 and
SMBus V2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3882-1.
Clock stretching will only occur if enabled and the bus
communication speed exceeds 100kHz.
PMBus protocols for busy devices are well accepted
standards but can make writing system level software
somewhat complex. The part provides three handshaking
status bits which reduce this complexity while enabling
robust system level communication. The three hand
Figure 45. Write Command Data Processing
DECODER
CMD
INTERNAL
PROCESSOR
WRITE COMMAND
DATA BUFFER
PAGE
CMDS
0x00
0x21
0xFD
38821 F45
x1
•
•
•
•
•
•
MFR_RESET
VOUT_COMMAND
S
CALCULATIONS
PENDING
PMBus
WRITE
R
FETCH,
CONVERT
DATA
AND
EXECUTE
DATA
MUX
