Linear Technology Analog Devices LTC3882-1, Datasheet

Page: 62 / 108

LTC3882-1
62
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
The LTC3882-1 address is selected based on the program-
ming of the two configuration pins ASEL0 and ASEL1
according to Table 11. ASEL0 programs the bottom four
bits of the device address for the LTC3882-1, and ASEL1
programs the three most-significant bits. Either portion of
the address can also be retrieved from the MFR_ADDRESS
value in EEPROM. If both pins are left open, the full 7-bit
MFR_ADDRESS value stored in EEPROM is used to deter-
mine the device address. In the 4-phase example above,
it is recommended that one or both ASEL n pins on both
parts be programmed to create two unique addresses. The
LTC3882-1 also responds to 7-bit global addresses 0x5A
and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS
should not be set to either of these values.
Table 11. ASEL n Resistor Programming
R
TOP
(kΩ) R
BOT
(kΩ)
ASEL1 ASEL0
LTC3882-1 DEVICE
ADDRESS BITS[6:4]
LTC3882-1 DEVICE
ADDRESS BITS[3:0]
BINARY HEX BINARY HEX
0 or Open Open from EEPROM from EEPROM
10 23.2 1111 F
10 15.8 1110 E
16.2 20.5 1101 D
16.2 17.4 1100 C
20 17.8 1011 B
20 15 1010 A
20 12.7 1001 9
20 11 1000 8
24.9 11.3 111 7 0111 7
24.9 9.09 110 6 0110 6
24.9 7.32 101 5 0101 5
24.9 5.76 100 4 0100 4
24.9 4.32 011 3 0011 3
30.1 3.57 010 2 0010 2
30.1 1.96 001 1 0001 1
Open 0 000 0 0000 0
Internal Regulator Outputs
The V
DD33
pin provides supply current for much of the
internal LTC3882-1 analog circuitry at a nominal value of
3.3V. The LTC3882-1 features an internal linear regulator
that can be used to supply 3.3V to V
DD33
from a higher
voltage V
CC
supply (up to 12V nominal). Use of this LDO is
optional. The LTC3882-1 will also accept an external 3.3V
supply attached to this pin if V
CC
and V
DD33
are shorted. If
the internal 3.3V LDO is used, it can supply a peak current
of 85mA (including internal consumption), and the V
DD33
regulator output must be bypassed to GND with a low ESR
X5R or X7R ceramic capacitor with a value of 2.2μF. If an
external source supplies V
DD33
, a local low ESR bypass
capacitor with a value between 0.01μF and 0.1μF should
be placed directly between the V
DD33
and GND pins.
Do not draw more than 20mA from the internal 3.3V regula-
tor for the host system, governed by IC power dissipation
as discussed in the next section. This limit includes current
required for external pull up resistors for the LTC3882-1
that are terminated to V
DD33
.
V
DD33
powers a second internal 2.5V LDO whose output
is present on V
DD25
. This 2.5V supply provides power for
much of the internal processor logic on the LTC3882-1. The
V
DD25
output should be bypassed directly to GND with a
low ESR X5R or X7R ceramic capacitor with a value of 1μF
or greater. Do not draw any external system current from
this supply beyond that required for LTC3882-1 specific
configuration resistor dividers.
IC Junction Temperature
The user must ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC3882-1 package (
θ
JA
)
is 33°C/W, provided the exposed pad is in good thermal
contact with the PCB. The actual thermal resistance in the
application will depend on forced air cooling and other heat
sinking means, especially the amount of copper on the
PCB to which the LTC3882-1 is attached. The following
formula may be used to estimate the maximum average
power dissipation P
D
(in watts) of the LTC3882-1 when
V
CC
is supplied externally.
P
D
= V
CC
(0.024 + f
PWM
• 1.6e-5 + I
EXT
+ I
RC25
)
where:
I
EXT
= total external load drawn from V
DD33
, including
local pull-up resistors, in amps
I
RC25
= total current drawn from V
DD25
by LTC3882-1
configuration resistor dividers, in amps
and the
PWM
frequency f
PWM
is given in kHz