Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 6 Clock Generation Circuit
FEUL610Q111 6-12
6.4.2 Functioning PB0 (OUTCLK) as the High speed clock output
Set PB0MD1 bit (bit0 of PBMOD1 register) to “1” for specifying the low speed clock output as the tertiary function of
PB0.
Reg. name PBMOD1 register (Address: 0F25DH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7MD1 PB6MD1 PB5MD1 PB4MD1 PB3MD1 PB2MD1 PB1MD1 PB0MD1
Data * * * * * * * 1
Reg. name PBMOD0 register (Address: 0F25CH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7MD0 PB6MD0 PB5MD0 PB4MD0 PB3MD0 PB2MD0 PB1MD0 PB0MD0
Data * * * * * * * 0
Set PB0C1 bit (bit0 of PBCON1 register) to “1” and set PB0C0 bit(bit0 of PBCON0 register) to “1”, and set PB0DIR
bit(bit0 of PBDIR register) to “0”for specifying the PB0 as CMOS output.
Reg. name PBCON1 register (Address: 0F25BH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1
Data * * * * * * * 1
Reg. name PBCON0 register (Address: 0F25AH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0
Data * * * * * * * 1
Reg. name PBDIR register (Address: 0F259H)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7DIR PB6DIR PB5DIR PB4DIR PB3DIR PB2DIR PB1DIR PB0DIR
Data * * * * * * * 0
Data of PB0D bit (bit0 of PBD register) does not affect to the high speed clock output function, so don’t care the data for
the function.
Reg. name PBD register (Address: 0F258H)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7D PB6D PB5D PB4D PB3D PB2D PB1D PB0D
Data * * * * * * * **
- : Bit does not exist.
* : Bit not related to the high speed clock function
** : Don’t care the data.