Lapis ML610Q111, User Manual

Page: 120 / 402

ML610Q111/ML610Q112 User’s Manual
Chapter 8 Timers
FEUL610Q111 8-17
8.2.13 Timer F Counter Register (TMFC)
Address: 0F369H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
TMFC TFC7 TFC6 TFC5 TFC4 TFC3 TFC2 TFC1 TFC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TMFC is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TMFC is performed, TMFC is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode, both the low-order TMEC and the high-order TMFC are set to “00H” when write operation to either
the low-order or the high-order is performed. Write to the register while the timer F is stopped (in 8-bit timer mode,
TFSTAT, TFTGEN and TFRUN of TMFCON1 are “0”, in 16-bit timer mode, TESTAT, TETGEN and TERUN of
TMACON1 are “0”).
When reading TMFC in 16-bit timer mode, be sure to read TMEC first since the count value of TMFC is stored in the
TMFC latch when TMEC is read.
During timer operation, the contents of TMFC may not be read depending on the conditions of the timer clock and the
system clock.
Table 8-6 shows whether a TMFC read is enabled or disabled during timer operation for each condition of the timer clock
and system clock.
Table 8-6 TMFC Read Enable/Disable during Timer Operation
Timer clock
TFCK
System clock
SYSCLK
TMFC read enable/disable
LSCLK LSCLK Read enabled
LSCLK HSCLK
Read enabled. However, to prevent the reading of undefined
data during counting up, read consecutively TMFC twice until the
last data matched the previous data.
HTBCLK LSCLK Read disabled
HTBCLK HSCLK Read enabled
1/2 HTBCLK to
1/64 HTBCLK
LSCLK
Read disabled.
1/2 HTBCLK to
1/64 HTBCLK
HSCLK
Read enabled. However, to prevent the reading of undefined
data during counting up, read consecutively TMFC twice until the
last data matched the previous data.
PLLCLK LSCLK
Read disabled.
PLLCLK HSCLK
Read disabled.