Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 12 UART
FEUL610Q111 12-17
12.3.5 Receive Operation
Select the received data pin using the UnRSEL bit of the UARTn mode register 0 (UAnMOD0). Select the receive mode by
setting the UnIO bit of the UARTn mode register 0 (UAnMOD0) to "1". Then, set the UnEN bit of the UARTn control
register (UAnCON) to "1" to start receiving data.
Figure 12-6 shows the operation timing for reception.
When receive operation starts, the LSI checks the data sent to the input pin RXDn and waits for the arrival of a start bit.
When detecting a start bit (

), the LSI generates the internal transfer clock of the baud rate set with the start bit detect
point as a reference and starts receive operation.
The shift register shifts in the data input to RXDn on the rising edge of the internal transfer clock. The data and parity bit
are shifted into the shift register and 5- to 8- bit received data is transferred to the transmit/receive buffer (UAnBUF)
concurrently with the fall of the internal transfer clock of

.
The LSI requests a UARTn interrupt on the rising edge of the internal transfer clock subsequent to the internal transfer
clock by which the received data was fetched (

) and checks for a stop bit error and a parity bit error. When an error is
detected, the LSI sets the corresponding bit of the UARTn status register (UAnSTAT) to “1”.
Parity error : SnPER = “1”
Overrun error : SnOER = “1”
Framing error : SnFER = “1”
The rise of the internal transfer clock is set so that it may fall into the middle of the bit interval of the received data.
Reception continues until the UnEN bit is reset to “0” by the program. When the UnEN bit is reset to “0” during reception,
the received data may be destroyed. When the UnEN bit is reset to “0” during the “UnEN reset enable period” in Figure
12-6, the received data is protected.
Figure 12-6 Operation Timing in Reception
Note :
UnOER becomes “1” when the next received data is overwritten before the received data of transmit/receive buffer
(UAnBUF) is read. When the reception stops/restarts by UnEN , UnOER becomes "1" if the last received data is not read.
Therefore always read the UAnBUF even if the received data is unnecessary when the reception completed.
UnEN
RXDn
UAnINT
UnPER
UnOER
BRT
Start
0
1 2 7
Parity
Start
BRT
Stop
0 1 6
7
Parity
Stop
UnEN reset enable period
2nd data
1st data
Detection of start bit








Parity error, overrun error,
framing error detected
Request for UARTn interrupt


Stop receiving
because the start bit
is not loaded.
↓
: Parity error
↓
: Overrun error
Start
0 2 7
Parity 1 Start
Stop 0
1 6 7
Parity
Stop
Internal
transfer clock
Shift register
(Input stage)
TX/RX buffer