Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 6 Clock Generation Circuit
FEUL610Q111 6-1
6 Clock Generation Circuit
6.1 Overview
The clock generation circuit generates and provides a low-speed clock (LSCLK), high-speed clock (HSCLK), built-in PLL
clock (PLLCLK), high-speed oscillation clock (OSCLK), system clock (SYSCLK), low-speed output clock (LSCLK), and
high-speed output clock (OUTCLK). LSCLK, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a
basic operation clock of CPU, and LSCLK/OUTCLK is a clock that is output from a port.
For the LSCLK and OUTCLK output port, see Chapter 15, “Port A” and Chapter 16, “Port B”.
Additionally, for the STOP mode described in this chapter, see Chapter 4, “MCU Control Function”.
6.1.1 Features
•
Low-speed clock generation circuit:
−
Built-in RC oscillation (32.768kHz) mode
•
High-speed clock generation circuit: Software selection
−
Built-in PLL oscillation mode
−
External clock input mode
6.1.2 Configuration
Figure 6-1 shows the configuration of the clock generation circuit.
FCON0 : Frequency control register 0
FCON1 : Frequency control register 1
Figure 6-1 Configuration of Clock Generation Circuit
Note :
This LSI starts operation with the 32.768kHz RC oscillation clock after power-on or a system reset. At initialization by
software, set the FCON0, FCON1 register to switch the clock to a required one.
High-speed
clock generation
circuit
PA2,PB6/CLKIN
Low-speed clock
(LSCLK)
High-speed clock
(HSCLK)
System clock
(SYSCLK)
Data bus
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
High-speed output clock
(PA0,PB0/OUTCLK)
OSCLK
Low-speed
clock generation
circuit
Low-speed output clock
(PA1,PB7/LSCLK)
FCON0, FCON1
PLL
1/2
High-speed oscillation clock
(OSCLK)
Built-in PLL clock
(PLLCLK)