Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 12 UART
FEUL610Q111 12-18
12.3.5.1 Detection of Start Bit
The Start bit is sampled using the baud rate generator clock (LSCLK, HSCLK) which selected by UnCK1, UnCK0 bits of
UARTn mode register 0 (UAnMOD0). Therefore, the start bit detection may be delayed for one cycle of the baud rate
generate clock at the maximum.
Figure 12-7 shows the start bit detection timing.
Figure 12-7 Start Bit Detection Timing (Positive Logic)
12.3.5.2 Sampling Timing
When the start bit is detected, the receive data that has been input to RXDn is sampled roughly at the middle of the baud
rate and shifted into the shift register.
This sampling timing, where the receive data is sampled to be shifted into the shift register, can be adjusted by one clock
pulse of the baud rate generator clock by using the UnRSS bit of the UARTn mode register 0 (UAnMOD0). Figure 12-8
shows the relationship between the UnRSS bit and sampling timing.
(1) When the baud rate generator count value is “7” (odd number)
(2) When the baud rate generator count value is “8” (even number)
Figure 12-8 Relationship between UnRSS Bit and Sampling Timing
Baud rate generator clock
RXDn
0 3 2 7 0 3 2 7
Sampling timing
UnRSS=1 UnRSS=0
Count value = 8
Baud rate generator clock
RXDn
0 3 2 6 0 3 2 6
Sampling timing
UnRSS=1 UnRSS=0
Count value = 7
Start bit
RXDn
Baud rate generator
sampling by clock
Maximum one-cycle delay