Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 10 PWM
FEUL610Q111 10-30
10.2.27 PWMF Counter Registers (PWFCH, PWFCL)
Address: 0F970H
Access: R/W
Access size: 8/16 bits
Initial value: 00H
7 6 5 4 3 2 1 0
PWFCL PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Address: 0F971H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
PWFCH PFC15 PFC14 PFC13 PFC12 PFC11 PFC10 PFC9 PFC8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
PWFCL and PWFCH are special function registers (SFRs) that function as 16-bit binary counters.
When data is written to either PWFCL or PWFCH, PWFCL and PWFCH is set to “0000H”. The data that is written is
meaningless. Write data while the PWM is stopped(PFSTAT, PFTGEN and PFRUN of PWFCON1 are “0”).
When data is read from PWFCL, the value of PWFCH is latched. When reading PWFCH and PWFCL, use a word type
instruction or pre-read PWFCL.
The contents of PWFCH and PWFCL during PWMF0 to 2 operation cannot be read depending on the combination of the
PWM clock and system clock. Table 10-4 shows PWFCH and PWFCL read enable/disable for each combination of the
PWM clock and system clock.
Table 10-4 PWFCH and PWFCL Read Enable/Disable during PWMF Operation
PWM clock
PFCK
System clock
SYSCLK
PWFCH and PWFCL read enable/disable
LSCLK LSCLK
Read enabled
LSCLK HSCLK
Read enabled. However, to prevent the reading of undefined
data during counting, read consecutively PWFCH or PWFCL
twice until the last data matched the previous data.
HTBCLK LSCLK
Read disabled
HTBCLK HSCLK Read enabled
PLLCLK
(16.384MHz)
LSCLK
Read disabled
HSCLK