Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 8 Timers
FEUL610Q111 8-16
8.2.12 Timer E Counter Register (TMEC)
Address: 0F361H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
TMEC TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TMEC is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TMEC is performed, TMEC is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode, both the low-order TMEC and the high-order TMFC are set to “00H” when write operation to either
the low-order or the high-order is performed. Write to the register while the timer E is stopped (TESTAT, TETGEN and
TERUN of TMECON1 are "0").
During timer operation, the contents of TMEC may not be read depending on the conditions of the timer clock and the
system clock.
Table 8-5 shows whether a TMEC read is enabled or disabled during timer operation for each condition of the timer clock
and system clock.
Table 8-5 TMEC Read Enable/Disable during Timer Operation
Timer clock
TECK
System clock
SYSCLK
TMEC read enable/disable
LSCLK LSCLK Read enabled
LSCLK HSCLK
Read enabled. However, to prevent the reading of undefined
data during counting up, read consecutively TMEC twice until the
last data matched the previous data.
HTBCLK LSCLK Read disabled
HTBCLK HSCLK Read enabled
1/2 HTBCLK to
1/64 HTBCLK
LSCLK
Read disabled.
1/2 HTBCLK to
1/64 HTBCLK
HSCLK
Read enabled. However, to prevent the reading of undefined
data during counting up, read consecutively TMEC twice until the
last data matched the previous data.
PLLCLK LSCLK Read disabled.
PLLCLK HSCLK
Read disabled.