ML610Q111/ML610Q112 User’s Manual
Chapter 18 Port D
FEUL610Q111
18-6
18.2.4 Port D Control Registers
0, 1 (PDCON0, PDCON1)
Address: 0F26AH
Access: R/W
Access size: 8/16 bits
Initial value: 00H
7
6
5
4
3
2
1
0
PDCON0
―
―
PD5C0
PD4C0
PD3C0
PD2C0
PD1C0
PD0C0
R/W
―
―
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Address: 0F26BH
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
PDCON1
―
―
PD5C1
PD4C1
PD3C1
PD2C1
PD1C1
PD0C1
R/W
―
―
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
PDCON0 and PDCON1 are special function registers (SFRs) to select input/output state of the Port D pin. The
input/output state is different between input mode and output mode. Input or output is selected by using the PDDIR
register.
[Description of Bits]
•
PD5C1-PD0C1, PD5C0-PD0C0
(bits 5
to 0)
The PD5C1 to PD0C1 pins and the PD5C0 to PD0C0 pins are used to select high-impedance output*, P-channel open
drain output, N-channel open drain output, or CMOS output in output mode and to select high-impedance input, input
with a pull-down resistor, or input with a pull-up resistor in input mode.
* High-impedance output means the status that both of H level output and L level output turn off.
Setting of PD0 pin
When output mode is selected
(PD0DIR bit = “0”)
When input mode is selected
(PD0DIR bit = “1”)
PD0C1
PD0C0
Description
0
0
High-impedance output (initial value)
High-impedance input
0
1
P-channel open drain output
Input with a pull-down resistor
1
0
N-channel open drain output
Input with a pull-up resistor
1
1
CMOS output
High-impedance input
Setting of PD1 pin
When output mode is selected
(PD1DIR bit = “0”)
When input mode is selected
(PD1DIR bit = “1”)
PD1C1
PD1C0
Description
0
0
High-impedance output (initial value)
High-impedance input
0
1
P-channel open drain output
Input with a pull-down resistor
1
0
N-channel open drain output
Input with a pull-up resistor
1
1
CMOS output
High-impedance input
Setting of PD2 pin
When output mode is selected
(PD2DIR bit = “0”)
When input mode is selected
(PD2DIR bit = “1”)
PD2C1
PD2C0
Description
0
0
High-impedance output (initial value)
High-impedance input
0
1
P-channel open drain output
Input with a pull-down resistor
1
0
N-channel open drain output
Input with a pull-up resistor
1
1
CMOS output
High-impedance input
Summary of Contents for ML610Q111
Page 1: ...ML610Q111 ML610Q112 User s Manual Issue Date Nov 16 2016 FEUL610Q111 05 ...
Page 14: ...Chapter 1 Overview ...
Page 26: ...Chapter 2 CPU and Memory Space ...
Page 34: ...Chapter 3 Reset Function ...
Page 38: ...Chapter 4 MCU Control Function ...
Page 53: ...Chapter 5 Interrupts INTs ...
Page 81: ...Chapter 6 Clock Generation Circuit ...
Page 95: ...Chapter 7 Time Base Counter ...
Page 103: ...Chapter 8 Timers ...
Page 145: ...Chapter 9 Watchdog Timer ...
Page 153: ...Chapter 10 PWM ...
Page 199: ...Chapter 11 Synchronous Serial Port ...
Page 212: ...Chapter 12 UART ...
Page 240: ...Chapter 13 I2 C Bus Interface Master ...
Page 254: ...Chapter 14 I2 C Bus Interface Slave ...
Page 269: ...Chapter 15 Port A ...
Page 279: ...Chapter 16 Port B ...
Page 291: ...Chapter 17 Port C ...
Page 303: ...Chapter 18 Port D ...
Page 312: ...Chapter 19 Port AB Interrupts ...
Page 317: ...Chapter 20 Successive Approximation Type A D Converter ...
Page 335: ...Chapter 21 Voltage Level Supervisor ...
Page 342: ...Chapter 22 Analog Comparator ...
Page 353: ...Chapter 23 Data Flash Memory ...
Page 373: ...Chapter 24 On chip Debug ...
Page 375: ...Appendixes ...
Page 393: ...Appendix E ...
Page 398: ...Revision History ...