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ML610Q111/ML610Q112 User’s Manual

Chapter 12 UART

FEUL610Q111

12-13

12.3 Description of Operation

12.3.1

Transfer Data Format

In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can
be selected as data bit. For the parity bit, “with parity bit”, “without parity bit”, “even parity”, or “odd parity” can be
selected. For the stop bit, “1 stop bit” or “2 stop bits” are available and for the transfer direction, “LSB first” or “MSB
first” are available for selection. For serial input/output logic, positive logic or negative logic can be selected.
All these options are set with the UARTn mode register

1 (UAnMOD1).

Figure 12-2 and Figure 12-3 show the positive logic input/output format and negative logic input/output format,
respectively.

Figure 12-2 Positive Logic Input/Output Format

Figure 12-3 Negative Logic Input/Output Format

Start

bit

1

2

3

4

5

6

7

8

Parity

bit

Data bit

1 frame

•1 frame

Max. ... 12 bits
Min. ... 7 bits

•Data bit length ... 8 to 5 bits variable

•Parity bit ... With or without parity bit selectable

Odd or even parity selectable

•Stop bit ... 1 or 2 stop bits selectable

Stop

bit

Stop

bit

Start

bit

1

2

3

4

5

6

7

8

Parity

bit

Data bit

1 frame

•1 frame

Max. ... 12 bits
Min. ... 7 bits

•Data bit length ... 8 to 5 bits variable

•Parity bit ... With or without parity bit selectable

Odd or even parity selectable

•Stop bit ... 1 or 2 stop bits selectable

Stop

bit

Stop

bit

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Summary of Contents for ML610Q111

Page 1: ...ML610Q111 ML610Q112 User s Manual Issue Date Nov 16 2016 FEUL610Q111 05 ...

Page 2: ... designed to be radiation tolerant 7 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representative transportation equipment i e cars ships trains primary communication equipment traffic lights fire crime prevention safety equipment medical systems servers solar cells and power transmission sy...

Page 3: ... and also on the specifications of the assembler language CCU8 User s Manual Description on the method of operating the compiler CCU8 Programming Guide Description on the method of programming CCU8 Language Reference Description on the language specifications DTU8 Debugger User s Manual Description on the method of operating the debugger DTU8 IDEU8 User s Manual Description on the integrated devel...

Page 4: ...logy H level 1 level Indicates high voltage signal levels VIH and VOH as specified by the electrical characteristics L level 0 level Indicates low voltage signal levels VIL and VOL as specified by the electrical characteristics Register description R W Indicates that Read Write attribute R indicates that data can be read and W indicates that data can be written R W indicates that data can be read ...

Page 5: ...on of Registers 3 2 3 2 1 List of Registers 3 2 3 2 2 Reset Status Register RSTAT 3 2 3 3 Description of Operation 3 3 3 3 1 Operation of System Reset Mode 3 3 Chapter 4 4 MCU Control Function 4 1 4 1 Overview 4 1 4 1 1 Features 4 1 4 1 2 Configuration 4 1 4 2 Description of Registers 4 2 4 2 1 List of Registers 4 2 4 2 2 Stop Code Acceptor STPACP 4 3 4 2 3 Standby Control Register SBYCON 4 4 4 2 ...

Page 6: ...Maskable Interrupt Processing 5 23 5 3 3 Software Interrupt Processing 5 23 5 3 4 Notes on Interrupt Routine 5 24 5 3 5 Interrupt Disable State 5 27 Chapter 6 6 Clock Generation Circuit 6 1 6 1 Overview 6 1 6 1 1 Features 6 1 6 1 2 Configuration 6 1 6 1 3 List of Pins 6 2 6 2 Description of Registers 6 2 6 2 1 List of Registers 6 2 6 2 2 Frequency Control Register 0 FCON0 6 3 6 2 3 Frequency Contr...

Page 7: ...CON0 8 18 8 2 15 Timer 9 Control Register 0 TM9CON0 8 19 8 2 16 Timer A Control Register 0 TMACON0 8 20 8 2 17 Timer B Control Register 0 TMBCON0 8 21 8 2 18 Timer E Control Register 0 TMECON0 8 22 8 2 19 Timer F Control Register 0 TMFCON0 8 23 8 2 20 Timer 8 Control Register 1 TM8CON1 8 24 8 2 21 Timer 9 Control Register 1 TM9CON1 8 25 8 2 22 Timer A Control Register 1 TMACON1 8 26 8 2 23 Timer B...

Page 8: ... 2 PWDCON2 10 17 10 2 15 PWMD Control Register 3 PWDCON3 10 18 10 2 16 PWME Period Registers PWEPL PWEPH 10 19 10 2 17 PWME Duty Registers PWEDL PWEDH 10 20 10 2 18 PWME Counter Registers PWECH PWECL 10 21 10 2 19 PWME Control Register 0 PWECON0 10 22 10 2 20 PWME Control Register 1 PWECON1 10 23 10 2 21 PWME Control Register 2 PWECON2 10 24 10 2 22 PWME Control Register 3 PWECON3 10 25 10 2 23 PW...

Page 9: ...ol Register UA0CON 12 4 12 2 5 UART1 Control Register UA1CON 12 4 12 2 6 UART0 Mode Register 0 UA0MOD0 12 5 12 2 7 UART1 Mode Register 0 UA1MOD0 12 6 12 2 8 UART0 Mode Register 1 UA0MOD1 12 7 12 2 9 UART1 Mode Register 1 UA1MOD1 12 8 12 2 10 UART0 Baud Rate Registers L H UA0BRTL UA0BRTH 12 9 12 2 11 UART1 Baud Rate Registers L H UA1BRTL UA1BRTH 12 10 12 2 12 UART0 Status Register UA0STAT 12 11 12 ...

Page 10: ... 13 3 3 Operation Waveforms 13 12 13 4 Specifying port registers 13 13 13 4 1 Functioning PB5 SCL and PB6 SDA as the I2C 13 13 Chapter 14 14 I2C Bus Interface Slave 14 1 14 1 Overview 14 1 14 1 1 Features 14 1 14 1 2 Configuration 14 1 14 1 3 List of Pins 14 2 14 2 Description of Registers 14 3 14 2 1 List of Registers 14 3 14 2 2 I2C Bus 1 Receive Register I2C1RD 14 4 14 2 3 I2C Bus 1 Slave Addre...

Page 11: ...gisters 0 PBMOD0 PBMOD1 16 9 16 3 Description of Operation 16 11 16 3 1 Input Output Port Functions 16 11 16 3 2 Primary Function except for Input Output Port 16 11 16 3 3 Secondary tertiary and fourthly functions 16 11 Chapter 17 17 Port C 17 1 17 1 Overview 17 1 17 1 1 Features 17 1 17 1 2 Configuration 17 2 17 1 3 List of Pins 17 3 17 2 Description of Registers 17 4 17 2 1 List of Registers 17 ...

Page 12: ... 8 SA ADC Result Register 3L SADR3L 20 7 20 2 9 SA ADC Result Register 3H SADR3H 20 7 20 2 10 SA ADC Result Register 4L SADR4L 20 8 20 2 11 SA ADC Result Register 4H SADR4H 20 8 20 2 12 SA ADC Result Register 5L SADR5L 20 9 20 2 13 SA ADC Result Register 5H SADR5H 20 9 20 2 14 SA ADC Result Register 6L SADR6L 20 10 20 2 15 SA ADC Result Register 6H SADR6H 20 10 20 2 16 SA ADC Result Register 7L SA...

Page 13: ...1 23 2 Description of Registers 23 2 23 2 1 List of Registers 23 2 23 2 2 Flash Address Register FLASHAL H 23 3 23 2 3 Flash Data Register FLASHDL H 23 4 23 2 4 Flash Control Register FLASHCON 23 5 23 2 5 Flash Accepter FLASHACP 23 6 23 2 6 Flash Segment Register FLASHSEG 23 7 23 2 7 Flash Self Register FLASHSLF 23 7 23 2 8 Flash Protection Register FLASHPRT 23 8 23 2 9 Flash Erase Abort Source Se...

Page 14: ...Chapter 1 Overview ...

Page 15: ...itional jump call return stack manipulations arithmetic shift and so on On Chip debug function Minimum instruction execution time 30 5µs 32 768kHz system clock 0 122µs 8 192MHz system clock Internal memory ML610Q111 Flash memory Program memory 24Kbyte 12K 16 bits including unusable 32 byte test data area Data flash memory 4Kbyte 2 K 16 bits RAM 2Kbyte 2K 8 bits ML610Q112 Flash memory Program memro...

Page 16: ...arity no parity odd parity even parity 1 stop bit 2 stop bits Positive logic negative logic selectable Built in baud rate generator I2 C Bus Interface Master function Standard mode 100 kbits s 8 MHz First mode 400 kbits s 8 MHz Slave function Standard mode 100 kbits s Synchronous Serial Port SSIO Master slave selectable LSB first MSB first selectable 8 bit length 16 bit length selectable Support S...

Page 17: ... 8 192MHz max Selection of high speed clock mode by software Built in PLL oscillation external clock Power management HALT mode Instruction execution by CPU is suspended peripheral circuits are in operating states STOP mode Stop of low speed oscillation and high speed oscillation Operations of CPU and peripheral circuits are stopped Clock gear The frequency of high speed system clock can be change...

Page 18: ...ntroller EA SP On Chip ICE Instruction Decoder BUS Controller Instruction Register INT PA0 to PA2 PB0 to PB7 Data bus Power RESET TEST ALU EPSW1 3 PSW ELR1 3 LR ECSR1 3 DSR CSR PC GREG 0 15 VDD VSS AIN0 to AIN5 AIN7 2 SDA SCK SOUT SIN PC4 to PC7 2 CMP0P CMP0M CMP1OUT CMP1P TEST RESET_N INT 1 RXD1 TXD1 TEST RESET_N INT 1 CMP0OUT INT 2 10bit ADC Analog Comparator x 2 Clock Generator VLS 1 INT 4 INT ...

Page 19: ...3 PD2 15 14 13 12 11 10 9 16 TESTF CMP1P AIN1 EXI1 PA1 TMFOUT LSCLK PWMD PB3 EXI7 SIN TXD1 PB2 EXI6 RXD1 PWME PB1 EXI5 AIN3 PWMD TXD0 TXD1 N C PB0 EXI4 AIN2 RXD0 PWMC OUTCLK CMP1OUT PD1 TEST 1 2 3 4 5 6 7 8 PA2 EXI2 PWME CLKIN CMP0OUT PWMF1 SDA CLKIN AIN4 PB6 N C VSS VDD AIN7 PC7 24 23 22 21 20 19 18 17 TXD1 TXD0 SOUT CMP0P PB4 PWMF2 SCL SCK RXD0 CMP0M PB5 PWMC PWMF0 LSCLK RXD1 AIN5 PB7 CMP0OUT CL...

Page 20: ...ock input CMP0 OUT O CMP0 output 3 4 PB0 EXI4 AIN2 RXD0 I O Input output port External interrupt ADC input UART0 data input External trigger PWM C O PWMC output OUTCL K O High speed clock output CMP1 OUT O CMP1 output 5 5 PB1 EXI5 AIN3 I O Input output port External interrupt ADC input External trigger PWM D O PWMD output TXD0 O UART0 data output TXD1 O UART1 data output 6 6 PB2 EXI6 RXD1 I O Inpu...

Page 21: ...WMF 1output 14 11 PC2 I O Input output port PWMF 2 O PWMF 2output 11 10 PC3 I O Input output port TMFO UT O timer F output 29 PC4 I O Input output port SCL I O I2C clock 28 PC5 I O Input output port SDA I O I2C data 26 PC6 AIN6 I O Input output port ADC input 23 PC7 AIN7 I O Input output port ADC input 31 PD0 I O Input output port 2 PD1 I O Input output port 10 PD2 I O Input output port 12 PD3 I O...

Page 22: ...xternal interrupt EXI0 to 2 EXI4 to 7 I External maskable interrupt input pins Interrupt enable and edge selection can be performed for each bit by software These pins are used as the primary functions of the PA0 PA2 and PB0 PB3 pins Primary Positive Negative Synchronous Serial Port SSIO SIN I Synchronous serial data input pin This pin is used as the secondary function of the PB3 pin Secondary Pos...

Page 23: ...e negative Successive approximation type A D converter AIN0 I Channel 0 analog input for successive approximation type A D converter This pin is used as the primary function of the PA0 pin Primary AIN1 I Channel 1 analog input for successive approximation type A D converter This pin is used as the primary function of the PA1 pin Primary AIN2 I Channel 2 analog input for successive approximation ty...

Page 24: ... I O Description Primary Secondary Tertiary Quaternary Logic For testing TEST I O Input output pin for testing A pull down resistor is internally connected Positive TESTF Test pin for flash memory A pull down resistor is internally connected Power supply VSS Negative power supply pin VDD Positive power supply pin ...

Page 25: ...ecommended pin termination RESET_N Open TEST Open TESTF Open PA0 to PA2 Open PB0 to PB7 Open PC0 to PC7 Open PD0 to PD5 Open N C Open Note It is recommended to set the unused input ports and input output ports to the inputs with pull down resistors pull up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input settin...

Page 26: ...Chapter 2 CPU and Memory Space ...

Page 27: ...112 has 32 Kbyte 16 Kword capacity Figure 2 1 shows the configuration of the program memory space of the ML610Q111 Figure 2 2 shows the configuration of the program memory space of the ML610Q112 CSR PC Segment 0 0 0000H Vector Table Area or Program Code ROM Window Area 0 00FFH 0 0100H Program Code Area or ROM Window Area 0 5FDFH 0 5FE0H 0 5FFFH Test Data Area 8bit Figure 2 1 Configuration of Progr...

Page 28: ...32 bytes 16 words test data area 0 7FE0H to 0 7FFFH of the Segment 0 this area cannot be used as a program code area The address 0 7FE0H to 0 7FFFH in the test area is write able and erase able Fill the area with 0FFH If data in the area is uncertain or other data i e not 0FFH operating with the code can not be guaranteed Set 0FFFFH data BRK instruction by using HTU8 program development support so...

Page 29: ... the configuration of the data memory space of the ML610Q111 Figure 2 4 shows the configuration of the data memory space of the ML610Q112 DSR Data address 0 0000H 0 5FFFH 0 6000H 0 0DFFFH Segment 0 DSR Data address Segment 2 ROM Window Area 2 0000H 2 0FFFH Data Flash Area 4 KB 2 1000H Unused Area Unused Area 0 0E000H 0 0E7FFH RAM Area 2 KB 0 0E800H Unused Area 0 0F000H 0 0FFFFH SFR Area 2 0FFFFH 8...

Page 30: ...gure 2 4 Configuration of Data Memory Space of the ML610Q112 Notes The contents of the 4 Kbyte RAM area are undefined at power on and system reset Initialize this area by software Although segment 0 of the program memory space and segment 0 of the data memory space are separate space the contents of segment 0 of the program memory space can read via ROM Window area of the data space Segment 8 is a...

Page 31: ... ML610Q112 User s Manual Chapter 2 CPU and Memory Space FEUL610Q111 2 5 2 4 Instruction Length The length of an instruction is 16 bits 2 5 Data Type The data types supported include byte 8 bits and word 16 bits ...

Page 32: ...12 User s Manual Chapter 2 CPU and Memory Space FEUL610Q111 2 6 2 6 Description of Registers 2 6 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F000H Data segment register DSR R W 8 00H ...

Page 33: ...ue 0 0 0 0 0 0 0 0 DSR is a special function register SFR to retain a data segment address For details of DSR see nX U8 100 Core Instruction Manual Description of Bits DSR3 DSR0 bits 3 0 DSR3 DSR2 DSR1 DSR0 Description 0 0 0 0 Data segment 0 initial value 0 0 0 1 Prohibited 0 0 1 0 Data segment 2 0 0 1 1 Prohibited 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Data segment 8 1 0 0 1 Prohibited 1 0 1 0 D...

Page 34: ...Chapter 3 Reset Function ...

Page 35: ...1 1 Features The RESET_N pin has an internal pull up resistor 46 8ms 62 5ms 125ms 250ms 1sec 4 sec or 16sec can be selected as the watchdog timer WDT second overflow period Built in reset status register RSTAT indicating the reset generation causes Only the CPU is reset by the BRK instruction the SFR area are not reset 3 1 2 Configuration Figure 3 1 shows the configuration of the reset generation ...

Page 36: ... the power on reset is generated This bit is set to 1 when powered on POR Description 0 Power on reset not generated 1 Power on reset generated WDTR bit 2 The WDTR is a flag that indicates that the watchdog timer reset is generated This bit is set to 1 when the reset by overflow of the watchdog timer is generated WDTR Description 0 Watchdog timer reset not occurred 1 Watchdog timer reset occurred ...

Page 37: ...oftware reset due to execution of the BRK instruction See Appendix A Registers for the initial values of the SFRs 2 CPU is initialized All the registers in CPU are initialized The contents of addresses 0000H and 0001H in the program memory are set to the stack pointer SP The contents of addresses 0002H and 0003H in the program memory are set to the program counter PC However when the interrupt lev...

Page 38: ...Chapter 4 MCU Control Function ...

Page 39: ...e reducing the current consumption 4 1 1 Features HALT mode where the CPU stops operating and only the peripheral circuit is operating STOP mode where both low speed oscillation and high speed oscillation stop Stop code acceptor function which controls transition to STOP mode Block control function which power downs the circuits of unused peripherals reset registers and stop clock supplies 4 1 2 C...

Page 40: ...s Name Symbol Byte Symbol Word R W Size Initial value 0F008H Stop code acceptor STPACP W 8 00H 0F009H Standby control register SBYCON W 8 00H 0F02AH Block control register 2 BLKCON2 R W 8 00H 0F02CH Block control register 4 BLKCON4 R W 8 00H 0F02EH Block control register 6 BLKCON6 R W 8 00H 0F02FH Block control register 7 BLKCON7 R W 8 00H ...

Page 41: ...TOP mode is disabled When another instruction is executed between the instruction that writes 5nH to STPACP and the instruction that writes 0AnH the entering the STOP mode is enabled after 0AnH is written However if data other than 0AnH is written to STPACP after 5nH is written the 5nH write processing becomes invalid so that data must be written again starting from 5nH For failsafe we recommend c...

Page 42: ...STOP mode is enabled by using STPACP when the STP bit is set to 1 the mode is changed to the STOP mode When the interrupt request enabled by the interrupt enable register IE0 IE7 is issued the STP bit is set to 0 and the LSI returns to the program run mode When the state of entering the STOP mode is disabled STP bit does not change to 1 STP HLT Description 0 0 Program run mode initial value 0 1 HA...

Page 43: ...us Interface Slave DI2C1 Description 0 Enables the operation of I 2 C bus Interface Slave initial value 1 Disables the operation of I 2 C bus Interface Slave DI2C0 bit 7 DI2C0 controls the operation of I2 C bus Interface Master DI2C0 Description 0 Enables the operation of I 2 C bus Interface Master initial value 1 Disables the operation of I 2 C bus Interface Master Note If the appropriate bit is ...

Page 44: ...r are reset and turned off DSAD Description 0 Enables operating SA type A D converter initial value 1 Disables operating SA type A D converter Note If the appropriate bit is set to 1 operation disabled the relevant block will be reset all registers are initialized and the clock of the relevant block will stop When this bit is set to 1 the writing to all the registers of the relevant block will be ...

Page 45: ...ontrols the operation of the Timer9 DTM9 Description 0 Enables the operation of the Timer9 initial value 1 Disables the operation of the Timer9 DTMA bit 2 DTMA controls the operation of the TimerA DTMA Description 0 Enables the operation of the TimerA initial value 1 Disables the operation of the TimerA DTMB bit 3 DTMB controls the operation of the TimerB DTMB Description 0 Enables the operation o...

Page 46: ...are initialized and the clock of the relevant block will stop When this bit is set to 1 the writing to all the registers of the relevant block will be invalid an initial value is read when a register is read To use the function of the relevant block reset enable operation the appropriate bit of the block control register to 0 Refer to Chapter 8 Timers for details of the Timer operation ...

Page 47: ...nitial value 1 Disables the operation of the PWMD DPWE bit 2 DPWE controls the operation of the PWME DPWE Description 0 Enables the operation of the PWME initial value 1 Disables the operation of the PWME DPWF bit 3 DPWF controls the operation of the PWMF DPWF Description 0 Enables the operation of the PWMF initial value 1 Disables the operation of the PWMF Note If the appropriate bit is set to 1 ...

Page 48: ...de The HALT mode is the state where the CPU interrupts execution of instructions and only the peripheral circuits are running When the HLT bit of the standby control register SBYCON is set to 1 the HALT mode is set When a WDT interrupt request or an interrupt request enabled by an interrupt enable register IE0 IE7 is issued the HLT bit is set to 0 on the falling edge of the next system clock SYSCL...

Page 49: ...d oscillation does not start When an interrupt request occurs the STOP mode is released after counting low speed clock LSCLK 32 times the mode is returned to the program run mode and the low speed clock LSCLK restarts supply to the peripheral circuits When the low speed clock LSCLK restart the high speed clocks OSCLK and HSCLK restarts supply to the peripheral circuits after counting for stabilizi...

Page 50: ...uits For the high speed oscillation start time TPLL see Appendix C Electrical Characteristics Figure 4 4 shows the operation waveforms in STOP mode when CPU operates with the high speed clock Figure 4 4 Operation Waveforms in STOP Mode When CPU Operates with High Speed Clock Note Since up to two instructions are executed during the period between STOP mode release and a transition to interrupt pro...

Page 51: ...es to the interrupt routine Table 4 2 Return Operation from STOP HALT Mode Maskable Interrupt ELEVEL MIE IEn m IRQn m Return operation from STOP HALT mode 0 Not returned from STOP HALT mode 0 1 0 1 1 After the mode is returned from STOP HALT mode the program operation restarts from the instruction following the instruction that sets the STP HLT bit to 1 The program operation does not go to the int...

Page 52: ... bits of block control registers are set to 1 and returns the initial value for read Ensure the bits are reset to 0 before using the peripherals to enable the operation BLKCON2 register controls enables or disables the operation of Synchronous Serial Port UART0 UART1 and I2C BLKCON4 register controls enables or disables the operation of SA type A D converter BLKCON6 register controls enables or di...

Page 53: ...Chapter 5 Interrupts INTs ...

Page 54: ...Chapter 11 Synchronous Serial Port Chapter 12 UART Chapter 13 I2 C Bus Interface Master Chapter 14 I2 C Bus Interface Slave Chapter 15 PortA Chapter 16 PortB Chapter 19 PortAB Interrupts Chapter 20 Successive Approximation Type A D Converter Chapter 21 Voltage Level Supervisor Chapter 22 Analog Comparator 5 1 1 Features 1 non maskable interrupt sources Internal source 30 maskable interrupt sources...

Page 55: ...nterrupt enable register 4 IE4 R W 8 00H 0F015H Interrupt enable register 5 IE5 R W 8 00H 0F016H Interrupt enable register 6 IE6 R W 8 00H 0F017H Interrupt enable register 7 IE7 R W 8 00H 0F018H Interrupt request register 0 IRQ0 R W 8 00H 0F019H Interrupt request register 1 IRQ1 R W 8 00H 0F01AH Interrupt request register 2 IRQ2 R W 8 00H 0F01BH Interrupt request register 3 IRQ3 R W 8 00H 0F01CH I...

Page 56: ...R W Initial value 0 0 0 0 0 0 0 0 IE0 is a special function register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE0 is not reset Description of Bits EVLS bit 6 EVLS is the enable flag for the voltage level supervisor interrupt VLSINT EVLS Description 0 Disabled initial value 1...

Page 57: ...t Description of Bits EPA0 bit 0 EPA0 is the enable flag for the input output port PA0 pin interrupt PA0INT EPA0 Description 0 Disabled initial value 1 Enabled EPA1 bit 1 EPA1 is the enable flag for the input output port PA1 pin interrupt PA1INT EPA1 Description 0 Disabled initial value 1 Enabled EPA2 bit 2 EPA2 is the enable flag for the input output port PA2 pin interrupt PA2INT EPA2 Description...

Page 58: ... EPB2 bit 6 EPB2 is the enable flag for the input output port PB2 pin interrupt PB2INT EPB2 Description 0 Disabled initial value 1 Enabled EPB3 bit 7 EPB3 is the enable flag for the input output port PB3 pin interrupt PB3INT EPB3 Description 0 Disabled initial value 1 Enabled ...

Page 59: ...t the corresponding flag of IE2 is not reset Description of Bits ESIO0 bit 0 ESIO0 is the enable flag for the synchronous serial port0 interrupt SIO0INT ESIO0 Description 0 Disabled initial value 1 Enabled ESAD bit 2 ESAD is the enable flag for the successive approximation type A D converter interrupt SADINT ESAD Description 0 Disabled initial value 1 Enabled EI2CS bit 6 EI2CS is the enable flag f...

Page 60: ...ial function register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE3 is not reset Description of Bits ETM8 bit 2 ETM8 is the enable flag for the timer 8 interrupt TM8INT ETM8 Description 0 Disabled initial value 1 Enabled ETM9 bit 3 ETM9 is the enable flag for the timer 9 inte...

Page 61: ...ter interrupt enable flag MIE is set to 0 but the corresponding flag of IE4 is not reset Description of Bits EUA0 bit 0 EUA0 is the enable flag for the UART0 interrupt UA0INT EUA0 Description 0 Disabled initial value 1 Enabled EUA1 bit 1 EUA1 is the enable flag for the UART1 interrupt UA1INT EUA1 Description 0 Disabled initial value 1 Enabled ECMP0 bit 6 ECMP0 is the enable flag for the comparator...

Page 62: ...ted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE5 is not reset Description of Bits ETME bit 4 ETME the enable flag for the timer E interrupt TMEINT ETME Description 0 Disabled initial value 1 Enabled ETMF bit 5 ETMF the enable flag for the timer F interrupt TMFINT ETMF Description 0 Disabled initial value 1 Enabled ETMA bit 6 ETMA the enable flag for the timer ...

Page 63: ... EPWC is the enable flag for the PWMC interrupt PWCINT EPWC Description 0 Disabled initial value 1 Enabled EPWD bit 1 EPWD is the enable flag for the PWMD interrupt PWDINT EPWD Description 0 Disabled initial value 1 Enabled EPWE bit 2 EPWE is the enable flag for the PWME interrupt PWEINT EPWE Description 0 Disabled initial value 1 Enabled EPWF bit 3 EPWF is the enable flag for the PWMF interrupt P...

Page 64: ...gister SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE7 is not reset Description of Bits E16H bit 0 E16H is the enable flag for the time base counter 16 Hz interrupt T16HINT E16H Description 0 Disabled initial value 1 Enabled E2H bit 3 E2H is the enable flag for the time base co...

Page 65: ...IE Each IRQ0 request flag is set to 1 regardless of the MIE value when an interrupt is generated By setting the IRQ0 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ0 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QWDT bit 0 QWDT is the request flag for the watchdog timer interrupt WDTINT QWDT Description 0 No ...

Page 66: ...s set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ1 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ1 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QPA0 bit 0 QPA0 is the request flag for the input port PA0 pin interrupt PA0INT QPA0 Description 0 No request initial value 1 Reque...

Page 67: ...g for the input port PB2 pin interrupt PB2INT QPB2 Description 0 No request initial value 1 Request QPB3 bit 7 QPB3 is the request flag for the input port PB3 pin interrupt PB3INT QPB3 Description 0 No request initial value 1 Request Note When an interrupt is generated by the write instruction to the interrupt request register IRQ1 or to the interrupt enable register IE1 the interrupt shift cycle ...

Page 68: ... corresponding flag of IRQ2 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QSIO0 bit 0 QSIO0 is the request flag for the synchronous serial port0 interrupt SIO0INT QSIO0 Description 0 No request initial value 1 Request QSAD bit 2 QSAD is the request flag for the successive approximation type A D converter interrupt SADINT QSAD Description 0 No request...

Page 69: ... register IE3 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ3 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ3 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QTM8 bit 2 QTM8 is the request flag for the timer 8 interrupt TM8INT QTM8 Description 0 No request initial value 1 R...

Page 70: ...1 by software an interrupt can be generated The corresponding flag of IRQ4 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QUA0 bit 0 QUA0 is the request flag for the UART0 interrupt UA0INT QUA0 Description 0 No request initial value 1 Request QUA1 bit 1 QUA1 is the request flag for the UART1 interrupt UA1INT QUA1 Description 0 No request initial value...

Page 71: ... 1 by software an interrupt can be generated The corresponding flag of IRQ5 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QTME bit 4 QTME is the request flag for the timer E interrupt TMEINT QTME Description 0 No request initial value 1 Request QTMF bit 5 QTMF is the request flag for the timer F interrupt TMFINT QTMF Description 0 No request initial ...

Page 72: ...IE is set to 1 By setting the IRQ6 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ6 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QPWC bit 0 QPWC is the request flag for the PWMC interrupt PWCINT QPWC Description 0 No request initial value 1 Request QPWD bit 1 QPWD is the request flag for the PWMD interrupt P...

Page 73: ...or the time base counter 32 Hz interrupt T32HINT Q32H Description 0 No request initial value 1 Request Note When an interrupt is generated by the write instruction to the interrupt request register IRQ6 or to the interrupt enable register IE6 the interrupt shift cycle starts after the next 1 instruction is executed ...

Page 74: ... set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ7 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ7 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits Q16H bit 0 Q16H is the request flag for the time base counter 16 Hz interrupt T16HINT Q16H Description 0 No request initial value 1 ...

Page 75: ...e interrupt I2CSINT 002CH 20 I 2 C Bus Interface Master interrupt I2CMINT 002EH 23 Timer 8 interrupt TM8INT 0034H 24 Timer 9 interrupt TM9INT 0036H 29 UART 0 interrupt UA0INT 0040H 30 UART 1 interrupt UA1INT 0042H 35 Comparator interrupt0 CMP0INT 004CH 36 Comparator interrupt1 CMP1INT 004EH 41 Timer E interrupt TMEINT 0058H 42 Timer F interrupt TMFINT 005AH 43 Timer A interrupt TMAINT 005CH 44 Tim...

Page 76: ... processing of program shifts to the interrupt destination 1 Transfer PC to ELR2 2 Transfer CSR to ECSR2 3 Transfer PSW to EPSW2 4 Set the ELEVEL field to 2 5 Load the interrupt start address into PC 5 3 3 Software Interrupt Processing A software interrupt is generated as required within an application program When the SWI instruction is performed within the program a software interrupt is generat...

Page 77: ...the end of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW A 1 2 When multiple interrupts are enabled Processing immediately after the start of interrupt routine execution Specify PUSH ELR EPSW to save the interrupt return address and the PSW status in the stack Processing at the end of interrupt rou...

Page 78: ...multiple interrupts are enabled Processing immediately after the start of interrupt routine execution Specify PUSH LR ELR EPSW to save the interrupt return address the subroutine return address and the EPSW status in the stack Processing at the end of interrupt routine execution Specify POP PC PSW LR instead of the RTI instruction to return the saved data of the interrupt return address to PC the ...

Page 79: ... B 2 2 When a subroutine is called for an interruption routine to a run time by a program Processing immediately after the start of interrupt routine execution PUSH LR ELR EPSW are specified and the return address of an interruption the return address of a subroutine and the status of EPSW are evacuated to a stack Processing at the end of interrupt routine execution Specifying POP PC PSW LR instea...

Page 80: ...ction at the beginning of the interrupt routine When the interrupt conditions are satisfied in this section an interrupt is generated immediately following the execution of the instruction at the beginning of the interrupt routine corresponding to the interrupt that has already been enabled Interrupt disabled state 2 Between the DSR prefix instruction and the next instruction When the interrupt co...

Page 81: ...Chapter 6 Clock Generation Circuit ...

Page 82: ...lt in RC oscillation 32 768kHz mode High speed clock generation circuit Software selection Built in PLL oscillation mode External clock input mode 6 1 2 Configuration Figure 6 1 shows the configuration of the clock generation circuit FCON0 Frequency control register 0 FCON1 Frequency control register 1 Figure 6 1 Configuration of Clock Generation Circuit Note This LSI starts operation with the 32 ...

Page 83: ...put pin Used for the tertiary function of the PA2 pin PB6 CLKIN I External clock input pin Used for the secondary function of the PB6 pin PA1 LSCLK O Low speed clock output pin Used for the tertiary function of the PA1 pin PB7 LSCLK O Low speed clock output pin Used for the secondary function of the PB7 pin 6 2 Description of Registers 6 2 1 List of Registers Address Name Symbol Byte Symbol Word R...

Page 84: ...h speed clock generation circuit PLL oscillation mode or external clock input mode can be selected The setting of OSCM0 can be changed only when high speed oscillation is being stopped ENOSC bit of FCON1 is 0 At system reset PLL oscillation mode is selected OSCM0 Description 0 Built in PLL oscillation mode initial value 1 External clock input mode PA2 PB6 CLKIN OUTC1 OUTC0 bits 5 4 The OUTC1 and O...

Page 85: ... LSCLK is selected for system clock SYSCLK Description 0 LSCLK initial value 1 HSCLK ENOSC bit 1 The ENOSC bit is used to select enable disable of the oscillation of the high speed clock oscillator ENOSC Description 0 Disables high speed oscillation initial value 1 Enables high speed oscillation LPLL bit 7 The LPLL bit is used as a flag to indicate the oscillation state of PLL oscillation When the...

Page 86: ...generation circuit is activated by the occurrence of power ON reset or port reset or WDT reset or VLS reset In starting by reset after waiting oscillation stable time 256 counts the clock is supplied to the peripheral circuit In the return from a STOP mode after waiting oscillation stable time 32 coounts a clock is supplied to a peripheral circuit Figure 6 2 Circuit Configuration of RC 32 768 kHz ...

Page 87: ...nal interrupt Then LSCLK is supplied to the peripheral circuits after a lapse of the low speed clock oscillation stabilization period 32 counts For STOP mode see Chapter 4 MCU Control Function Figure 6 3 shows the waveforms of the low speed clock generation circuit Figure 6 3 Operation of Low Speed Clock Generation Circuit Note After the power supply is turned on CPU starts operation with a low sp...

Page 88: ...cillation clock OSCLK When the frequency of a PLL oscillation clock is less than 16 384MHz 1 0 the LPLL flag of FCON1 is set to 1 In built in PLL oscillation mode OSCM0 0 OSCM1 1 supply of OSCLK high speed oscillation clock is started when the clock pulse which is generated by dividing the PLLCLK by 2 count reaches 8192 after oscillation is enabled ENOSC is set to 1 In built in PLL oscillation mod...

Page 89: ...h speed external clock input mode Figure 6 5 Circuit Configuration in High Speed External Clock Input Mode Notes If the PA2 PB6 CLKIN pin is left open in high speed external clock input mode excessive current can flow Therefore be sure to input a H level VDD or a L level VSS to the CLKIN pin The clock that is input must not exceed 8 192 MHz the guaranteed maximum operating frequency of the system ...

Page 90: ...riod of a low speed oscillation LSCLK and a high speed oscillation OSCLK clock in each mode HSCLK begins to be supplied to a peripheral circuit The oscillation stabilization period is the duration of 128 clock pulses in high speed external clock input mode and the duration of 8192 clock pulses in PLL oscillation mode Figure 6 6 shows the waveforms of the high speed clock generation circuit in bult...

Page 91: ...ed from a low speed clock to a high speed clock before the high speed clock HSCLK starts oscillation the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits System clock switching ENOSC 1 Wait until oscillation stabilizes TWAIT SYSCLK 1 High speed operation mode TWAIT 3ms bult in PLL oscillation mode TWAIT 1ms External clock input mode Start of high speed oscillation Sy...

Page 92: ...B1MD0 PB0MD0 Data 1 Set PB7C1 bit bit7 of PBCON1 register to 1 and set PB7C0 bit bit7 of PBCON0 register to 1 and set PB7DIR bit bit7 of PBDIR register to 0 for specifying the PB7 as CMOS output Reg name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1 Data 1 Reg name PBCON0 register Address 0F25AH Bit 7 6 5 4 3 2 1 0 Bit name PB7C0 PB6C0 ...

Page 93: ...gister to 1 and set PB0DIR bit bit0 of PBDIR register to 0 for specifying the PB0 as CMOS output Reg name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1 Data 1 Reg name PBCON0 register Address 0F25AH Bit 7 6 5 4 3 2 1 0 Bit name PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0 Data 1 Reg name PBDIR register Address 0F259H Bit 7 6 5 4 3 2 ...

Page 94: ...ON0 register to 0 and set PA2DIR bit bit2 of PADIR register to 1 for specifying the PA2 as input Reg name PACON1 register Address 0F253H Bit 7 6 5 4 3 2 1 0 Bit name PA2C1 PA1C1 PA0C1 Data 0 Reg name PACON0 register Address 0F252H Bit 7 6 5 4 3 2 1 0 Bit name PA2C0 PA1C0 PA0C0 Data 0 Reg name PADIR register Address 0F251H Bit 7 6 5 4 3 2 1 0 Bit name PA2DIR PA1DIR PA0DIR Data 1 Data of PA2D bit bi...

Page 95: ...Chapter 7 Time Base Counter ...

Page 96: ... T32KHZ to T1HZ signals by dividing the low speed clock LSCLK frequency HTBC generates the divided clock by dividing the high speed clock HSCLK frequency of HTBCLK 8 192MHz to 512kHz It is used as the timer s clock or the PWM s clocks Capable of generating 128Hz 32Hz 16Hz and 2Hz interrupts 7 1 2 Configuration Figure 7 1 and Figure 7 2 show the configuration of a low speed time base counter and a ...

Page 97: ...time base counter frequency divide register Figure 7 2 Configuration of High Speed Time Base Counter Note The frequency of HSCLK is changed by setting of SYSC1 bit and SYSC0 bit in the frequency control register 0 FCON0 HSCLK 8 192MHz HTBDR 1 n Counter R RESET 8 Data bus HTBCLK 8 192MHz to 512kHz ...

Page 98: ...EUL610Q111 7 3 7 2 Description of Registers 7 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F00AH Low speed time base counter register LTBR R W 8 00H 0F00BH High speed time base counter frequency divide register HTBDR R W 8 00H ...

Page 99: ... you reset LTBR please set it according to the following procedures 1 Disable interrupt by using DI instruction reset the master interrupt enable flag MIE to 0 2 Reset LTBR by writing any value to LTBR 3 Write 0 to each bit Q128H Q32H Q16H and Q2H of the interrupt request flag 6 and 7 IRQ6 and IRQ7 4 Enable interrupt by using EI instruction set MIE to 1 The T128Hz T1HZ output are the signal that t...

Page 100: ...TD0 bits are used to set the frequency divide ratio of the 4 bit 1 n counter The frequency divide ratios selectable include 1 1 to 1 16 HTD3 HTD2 HTD1 HTD0 Description Divide ratio Frequency of HTBCLK 1 0 0 0 0 1 16 initial value 512 kHz 0 0 0 1 1 15 546 kHz 0 0 1 0 1 14 586 kHz 0 0 1 1 1 13 630 kHz 0 1 0 0 1 12 682 kHz 0 1 0 1 1 11 744 kHz 0 1 1 0 1 10 820 kHz 0 1 1 1 1 9 910 kHz 1 0 0 0 1 8 1024...

Page 101: ...t read L R1 EA 2nd read CMP R0 R1 Comparison for LTBR BNE MARK To MARK when the values do not coincide Figure 7 3 Programming Example for Reading LTBR LTBR is reset when write operation is performed and the T128HZ to T1HZ outputs are set to 0 Write data is invalid Since an interrupt occurs if a falling edge occurs in the T128Hz to T1Hz outputs during writing to LTBR when you reset LTBR please set ...

Page 102: ... n counter the divided clock 1 16 HSCLK to 1 1 HSCLK selected by the high speed time base counter divide register HTBDR is generated as HTBCLK HTBCLK is used as an operaiton clock of the timer and PWM Figure 7 5 shows the output waveform of HTBCLK Figure 7 5 Output Waveform of HTBCLK High speed time base counter Divide register High speed clock HSCLK 1 n counter output HTBCLK 1 1 1 2 1 3 0FH 0EH 0...

Page 103: ...Chapter 8 Timers ...

Page 104: ...nd timer B or timer E and timer F can be used as a 16 bit timer For the timer clock the low speed clock LSCLK high speed time base clock HTBCLK or the divided clock PLLCLK can be selected The timer out signal of a timer 9 and Timer F TM9OUT TMFOUT can be outputted The output logic of the TM9OUT and TMFOUT signals can be switched to the positive or negative logic Continuous mode and one shot mode c...

Page 105: ...er 1 TMmD TMnD Timer data register TMmC TMnC Timer counter register Figure 8 1 1 2 the configuration of timers TMnC Data bus TMmINT LSCLK TMnCON0 TMnCON1 R Matched Comparator HTBCLK n 8 A m 9 B Write TMmC TnCK Write TMnC 8 8 8 8 TMnD TMmD TMmC R 8 8 16 8 8 16 TMmC latch Read TMnC OUT PA0 TM9OUT PC0 TM9OUT TM9NEG PLLCLK TMnC 8 Data bus TMnINT LSCLK TMnCON0 TMnCON1 R Matched TMnD Comparator 8 HTBCLK...

Page 106: ...tor output Figure 8 1 2 2 the configuration of timers TMnC Data bus TMmINT LSCLK TMnCON0 TMnCON1 R Matched Comparator HTBCLK Write TMmC TnCK Write TMnC 8 8 8 8 TMnD TMmD TMmC R 8 8 16 8 8 16 TMmC latch Read TMnC TMnCON2 TMnCON3 External trigger TnTG PA0 to PA2 PB0 to PB7 n E m F OUT PA1 TMFOUT PC3 TMFOUT TMFNEG PLLCLK CMP0 CMP1 TMnC 8 Data bus TMnINT LSCLK TMnCON0 TMnCON1 R Matched TMnD Comparator...

Page 107: ...e for the quaternary function of PA0 PA1 TnTG TMFOUT I O External trigger input of timer E F Timer F output pin Use for the quaternary function of PA1 PA2 TnTG I External trigger input of timer E F PB0 7 TnTG I External trigger input of timer E F PC0 TM9OUT I O Timer 9 output pin Use for the quaternary function of PC0 PC3 TMFOUT I Timer F output pin Use for the quaternary function of PC3 n E F ...

Page 108: ...N0 TMACON R W 8 16 00H 0F8EBH Timer A control register 1 TMACON1 R W 8 00H 0F8ECH Timer B data register TMBD TMBDC R W 8 16 0FFH 0F8EDH Timer B counter register TMBC R W 8 00H 0F8EEH Timer B control register 0 TMBCON0 TMBCON R W 8 16 00H 0F8EFH Timer B control register 1 TMBCON1 R W 8 00H 0F360H Timer E data register TMED TMEDC R W 8 16 0FFH 0F361H Timer E counter register TMEC R W 8 00H 0F362H Ti...

Page 109: ...ister SFR to set the value to be compared with the Timer 8 counter register TM8C value Note Set TM8D while the timer 8 is stopped T8STAT and T8RUN of TM8CON1 are 0 In 8 bit timer mode set one of 01H 0FFH to TM8D If it sets 00H the behavior is the same as setting 01H In 16 bit timer mode set one of 0001H 0FFFFH to TM9D TM8D If it sets 0000H the behavior is the same as setting 0001H Moreover there a...

Page 110: ... with the value of the Timer 9 counter register TM9C Note Set TM9D while the timer 9 is stopped in 8 bit timer mode T9STAT and T9RUN of TM9CON1 are 0 in 16 bit timer mode T8STAT and T8RUN of TM8CON1 are 0 In 8 bit timer mode set one of 01H 0FFH to TM9D If it sets 00H the behavior is the same as setting 01H In 16 bit timer mode set one of 0001H 0FFFFH to TM9D TM8D If it sets 0000H the behavior is t...

Page 111: ...ister SFR to set the value to be compared with the Timer A counter register TMAC value Note Set TMAD while the timer A is stopped TASTAT and TARUN of TMACON1 are 0 In 8 bit timer mode set one of 01H 0FFH to TMAD If it sets 00H the behavior is the same as setting 01H In 16 bit timer mode set one of 0001H 0FFFFH to TMBD TMAD If it sets 0000H the behavior is the same as setting 0001H Moreover there a...

Page 112: ... with the value of the Timer B counter register TMBC Note Set TMBD while the timer B is stopped in 8 bit timer mode TBSTAT and TBRUN of TMBCON1 are 0 in 16 bit timer mode TASTAT and TARUN of TMACON1 are 0 In 8 bit timer mode set one of 01H 0FFH to TMBD If it sets 00H the behavior is the same as setting 01H In 16 bit timer mode set one of 0001H 0FFFFH to TMBD TMAD If it sets 0000H the behavior is t...

Page 113: ...er SFR to set the value to be compared with the Timer E counter register TMEC value Note Set TMED while the timer E is stopped TESTAT TETGEN and TERUN of TMECON1 are 0 In 8 bit timer mode set one of 01H 0FFH to TMED If it sets 00H the behavior is the same as setting 01H In 16 bit timer mode set one of 0001H 0FFFFH to TMFD TMED If it sets 0000H the behavior is the same as setting 0001H Moreover the...

Page 114: ...the value of the Timer F counter register TMFC Note Set TMFD while the timer F is stopped in 8 bit timer mode TFSTAT TFTGEN and TFRUN of TMFCON1 are 0 in 16 bit timer mode TESTAT TETGEN and TERUN of TMECON1 are 0 In 8 bit timer mode set one of 01H 0FFH to TMFD If it sets 00H the behavior is the same as setting 01H In 16 bit timer mode set one of 0001H 0FFFFH to TMFD TMED If it sets 0000H the behav...

Page 115: ...0 During timer operation the contents of TM8C may not be read depending on the conditions of the timer clock and the system clock Table 8 1 shows whether a TM8C read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 1 TM8C Read Enable Disable during Timer Operation Timer clock T8CK System clock SYSCLK TM8C read enable disable LSCLK LSCLK R...

Page 116: ...r mode be sure to read TM8C first since the count value of TM9C is stored in the TM9C latch when TM8C is read During timer operation the contents of TM9C may not be read depending on the conditions of the timer clock and the system clock Table 8 2 shows whether a TM9C read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 2 TM9C Read Enabl...

Page 117: ...0 During timer operation the contents of TMAC may not be read depending on the conditions of the timer clock and the system clock Table 8 3 shows whether a TMAC read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 3 TMAC Read Enable Disable during Timer Operation Timer clock TACK System clock SYSCLK TMAC read enable disable LSCLK LSCLK R...

Page 118: ...er mode be sure to read TMAC first since the count value of TMBC is stored in the TMBC latch when TMAC is read During timer operation the contents of TMBC may not be read depending on the conditions of the timer clock and the system clock Table 8 4 shows whether a TMBC read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 4 TMBC Read Enab...

Page 119: ...are 0 During timer operation the contents of TMEC may not be read depending on the conditions of the timer clock and the system clock Table 8 5 shows whether a TMEC read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 5 TMEC Read Enable Disable during Timer Operation Timer clock TECK System clock SYSCLK TMEC read enable disable LSCLK LSC...

Page 120: ...bit timer mode be sure to read TMEC first since the count value of TMFC is stored in the TMFC latch when TMEC is read During timer operation the contents of TMFC may not be read depending on the conditions of the timer clock and the system clock Table 8 6 shows whether a TMFC read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 6 TMFC Re...

Page 121: ...alue 0 0 1 HTBCLK 0 1 0 1 64 HTBCLK 0 1 1 1 16 HTBCLK 1 0 0 1 8 HTBCLK 1 0 1 1 4 HTBCLK 1 1 0 1 2 HTBCLK 1 1 1 PLLCLK T89M16 bit 5 The T89M16 bit is used to select the operating mode of Timer 8 and Timer 9 In 8 bit timer mode each of Timer 8 and Timer 9 operates independently as a 8 bit timer In 16 bit timer mode Timer 8 and Timer 9 are connected and they operate as a 16 bit timer In 16 bit timer ...

Page 122: ... 1 2 HTBCLK and PLLCLK can be selected In cases where the 16 bit timer mode has been selected by setting T89M16 of TM8CON0 to 1 the values of T9CS2 T9CS1 T9CS0 are invalid T9CS2 T9CS1 T9CS0 Description 0 0 0 LSCLK initial value 0 0 1 HTBCLK 0 1 0 1 64 HTBCLK 0 1 1 1 16 HTBCLK 1 0 0 1 8 HTBCLK 1 0 1 1 4 HTBCLK 1 1 0 1 2 HTBCLK 1 1 1 PLLCLK T9NEG bit 6 The T9NEG bit is used to select the output logi...

Page 123: ...ial value 0 0 1 HTBCLK 0 1 0 1 64 HTBCLK 0 1 1 1 16 HTBCLK 1 0 0 1 8 HTBCLK 1 0 1 1 4 HTBCLK 1 1 0 1 2 HTBCLK 1 1 1 PLLCLK TABM16 bit 5 The TABM16 bit is used to select the operating mode of Timer A and Timer B In 8 bit timer mode each of Timer A and Timer B operates independently as a 8 bit timer In 16 bit timer mode Timer A and Timer B are connected and they operate as a 16 bit timer In 16 bit t...

Page 124: ...0 bits are used to select the operation clock of Timer B LSCLK HTBCLK 1 64 HTBCLK 1 16 HTBCLK 1 8 HTBCLK 1 4 HTBCLK 1 2 HTBCLK and PLLCLK can be selected In cases where the 16 bit timer mode has been selected by setting TABM16 of TMACON0 to 1 the values of TBCS2 TBCS1 TBCS0 are invalid TBCS2 TBCS1 TBCS0 Description 0 0 0 LSCLK initial value 0 0 1 HTBCLK 0 1 0 1 64 HTBCLK 0 1 1 1 16 HTBCLK 1 0 0 1 ...

Page 125: ...TBCLK 1 2 HTBCLK and PLLCLK can be selected TECS2 TECS1 TECS0 Description 0 0 0 LSCLK initial value 0 0 1 HTBCLK 0 1 0 1 64 HTBCLK 0 1 1 1 16 HTBCLK 1 0 0 1 8 HTBCLK 1 0 1 1 4 HTBCLK 1 1 0 1 2 HTBCLK 1 1 1 PLLCLK TEFM16 bit 2 The TEFM16 bit is used to select the operating mode of Timer E and Timer F In 8 bit timer mode each of Timer E and Timer F operates independently as a 8 bit timer In 16 bit t...

Page 126: ...f the TMFCON1 are 0 in 16 bit timer mode TESTAT TETGEN and TERUN of the TMECON1 are 0 Description of Bits TFCS2 TFCS1 TFCS0 bits 3 1 to 0 The TFCS2 TFCS1 TFCS0 bits are used to select the operation clock of Timer F LSCLK HTBCLK 1 64 HTBCLK 1 16 HTBCLK 1 8 HTBCLK 1 4 HTBCLK 1 2 HTBCLK and PLLCLK can be selected In cases where the 16 bit timer mode has been selected by setting TEFM16 of TMECON0 to 1...

Page 127: ...8RUN R W R R W Initial value 0 0 0 0 0 0 0 0 TM8CON1 is a special function register SFR to control the Timer 8 Description of Bits T8RUN bit 0 The T8RUN bit is used to control count stop start of Timer 8 T8RUN Description 0 Stops counting 1 Starts counting T8STAT bit 7 The T8STAT bit indicates counting stopped or counting in progress of Timer 8 T8STAT Description 0 Counting stopped 1 Counting in p...

Page 128: ...N bit 0 The T9RUN bit is used to control count stop start of Timer 9 When T89M16 of TM8CON0 is set to 1 and 16 bit timer mode is selected make sure that it is set to 0 Timer 9 is incremented caused by a Timer 8 overflow signal regardless of the value of T9RUN T9RUN Description 0 Stops counting 1 Starts counting T9STAT bit 7 The T9STAT bit indicates counting stopped or counting in progress of Timer...

Page 129: ...ARUN R W R R W Initial value 0 0 0 0 0 0 0 0 TMACON1 is a special function register SFR to control the Timer A Description of Bits TARUN bit 0 The TARUN bit is used to control count stop start of Timer A TARUN Description 0 Stops counting 1 Starts counting TASTAT bit 7 The TASTAT bit indicates counting stopped or counting in progress of Timer A TASTAT Description 0 Counting stopped 1 Counting in p...

Page 130: ...N bit 0 The TBRUN bit is used to control count stop start of Timer B When TABM16 of TMACON0 is set to 1 and 16 bit timer mode is selected make sure that it is set to 0 Timer B is incremented caused by a Timer A overflow signal regardless of the value of TBRUN TBRUN Description 0 Stops counting 1 Starts counting TBSTAT bit 7 The TBSTAT bit indicates counting stopped or counting in progress of Timer...

Page 131: ...e For the continuous mode when the timer count is stopped by the external trigger input and the interrupt is generated TERUN bit shows 0 as is controlled to stop counting When the timer count register coincides with the timer data register and the interrupt is generated TERUN bit shows 1 as is controlled to start keep counting Therefore reading TERUN bit can be used for recognizing which interrupt...

Page 132: ...ed or counting in progress of Timer F When TEFM16 of TMECON0 is set to 1 and 16 bit timer mode is selected 0 is read TFSTAT Description 0 Counting stopped 1 Counting in progress Note For the continuous mode when the timer count is stopped by the external trigger input and the interrupt is generated TFRUN bit shows 0 as is controlled to stop counting When the timer count register coincides with the...

Page 133: ... stop mode of the timer E counter TEST1 TEST0 Description Counter operation using the external input 0 0 Do not operate initial value 0 1 Start counting 1 0 Stop counting 1 1 Start stop counting TETRM1 TETRM0 bits 5 4 The TETRM1 and TETRM0 bits are used to select the start mode of the timer E counter This is valid only when the external input start and stop modes are selected When the timer count ...

Page 134: ...1 the values of TFST1 and TFST0 are invalid TFST1 TFST0 Description Counter operation using the external input 0 0 Do not operate initial value 0 1 Start counting 1 0 Stop counting 1 1 Start stop counting TFTRM1 TFTRM0 bits 5 4 The TFTRM1 and TFTRM0 bits are used to select the start mode of the timer F counter This is valid only when the external input start and stop modes are selected When the ti...

Page 135: ...TFOST bit 7 The TFOST bit is used to select continuous mode one shot mode of timer E In cases where the 16 bit timer mode has been selected by setting TEFM16 of TMECON0 to 1 the value of TFOST is invalid TFOST Description 0 Continuous mode initial value 1 One shot mode ...

Page 136: ... TESTSS TESTS2 TESTS1 TESTS0 bits 3 to 0 The TESTSS TESTS2 TESTS1 and TESTS0 bits are used to select the external input start stop pins of the timer E To use these bits to select the Port A and B pins use the Port A and B mode registers 0 1 PnMOD0 PnMOD1 to select the primary function and use the Port A and B direction PnDIR to set the input mode for the appropriate pins n A B TESTS2 TESTS1 TESTS0...

Page 137: ... bits 3 to 0 The TFSTSS TFSTS2 TFSTS1 and TFSTS0 bits are used to select the external input start stop pins of the timer F To use these bits to select the Port A and B pins use the Port A and B mode registers 0 1 PnMOD0 PnMOD1 to select the primary function and use the Port A and B direction PnDIR to set the input mode for the appropriate pins n A B When TEFM16 of TMECON0 is set to 1 and 16 bit ti...

Page 138: ...is 0 When the TnRUN bit is set to 1 again TMnC restarts incrementing from the previous value To initialize TMnC to 00H perform a write operation to TMnC The timer interrupt period TTMI is expressed by the following equation TTMI TMnD 1 n 8 to B E F TnCK Hz TMnD Timer 8 to B E F data register TMnD setting value 01H to 0FFH TnCK Clock frequency selected by the Timer 8 to B E F control register 0 TMn...

Page 139: ...nt value of TMnC and the preset value of a timer n data register TMnD is matched the output is returned to the initial value Figure 8 3 One shot mode Operation Timing Diagram of Timer 8 to B E F Note When the count value of TMnC and the value of a timer 8 to B E F data register TMnD are matched a TnRUN bit is cleared to 0 automatically TMnC XX 00 88 TMnD TMnINT TnSTAT Write TMnC TnCK TnRUN 01 02 8...

Page 140: ...n this state the TnRUN bit of the timer control register 1 TMnCON1 will be set to 1 by hardware The timer counter TMnC is set to an operating state TnSTAT is set to 1 on the first falling edge of the timer clock TnCK being selected by the Timer E F control register 0 TMnCON0 Then the timer counter TMnC starts incrementing on the 2nd falling edge When the count value of the timer counter register T...

Page 141: ...imer count is started by the external input rising edge timer count is stopped by software Note Although 0 is written in TnRUN since TnSTAT continues a counting operation to the falling edge of the next timer clock in the status of 1 TMnINT may occur TnRUN TMnC TMnD TMnINT TnSTAT Write TMnC TnCK n E F TTMI XX 00 88 01 02 87 88 00 5F 60 62 01 88 88 61 PADn external trigger input SYSCLK TnRUN TMnC T...

Page 142: ...by the software or automatically stopped in one shot timer mode always reset the timer counter register TMmC TMnC m 9 B F n 8 A E to 0000h by making a write operaton to the register data is don t care The write operation to either the higher byte register TMmC m 9 B F or lower byte register TMnC n 8 A E resets both registers If an intentional write of 00000h to reset the timer counter registers is...

Page 143: ...ddress 0F254H Bit 7 6 5 4 3 2 1 0 Bit name PA2MD0 PA1MD0 PA0MD0 Data 1 Set PA0C1 bit bit0 of PACON1 register to 1 and set PA0C0 bit bit0 of PACON0 register to 1 and set PA0DIR bit bit0 of PADIR register to 0 for specifying the PA0 as CMOS output Reg name PACON1 register Address 0F253H Bit 7 6 5 4 3 2 1 0 Bit name PA2C1 PA1C1 PA0C1 Data 1 Reg name PACON0 register Address 0F252H Bit 7 6 5 4 3 2 1 0 ...

Page 144: ...PCCON0 register to 1 and set PC3DIR bit bit3 of PCDIR register to 0 for specifying the PC3 as CMOS output Reg name PCCON1 register Address 0F263H Bit 7 6 5 4 3 2 1 0 Bit name PC7C1 PC6C1 PC5C1 PC4C1 PC3C1 PC2C1 PC1C1 PC0C1 Data 1 Reg name PCCON0 register Address 0F262H Bit 7 6 5 4 3 2 1 0 Bit name PC7C0 PC6C0 PC5C0 PC4C0 PC3C0 PC2C0 PC1C0 PC0C0 Data 1 Reg name PCDIR register Address 0F261H Bit 7 6...

Page 145: ...Chapter 9 Watchdog Timer ...

Page 146: ...e to a system reset mode For interrupts see Chapter 5 Interrupts and for WDT reset see Chapter 3 Reset Function 9 1 1 Features Free running cannot be stopped One of seven types of overflow periods 23 4ms 31 25ms 62 5ms 125ms 500ms 2s and 8s selectable by software Non maskable interrupt by the first overflow Reset generated by the second overflow 9 1 2 Configuration Figure 9 1 shows the configurati...

Page 147: ...chdog Timer FEUL610Q111 9 2 9 2 Description of Registers 9 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F00EH Watchdog timer control register WDTCON R W 8 00H 0F00FH Watchdog timer mode register WDTMOD R W 8 02H ...

Page 148: ...DTCON d7 d0 bits 7 0 This bit is used to write data to clear the WDT counter Write 5AH on the condition of WDP is 0 and write 0A5H on the condition of WDP is 1 Note When the WDT interrupt WDTINT occurs by the first WDT counter overflow the counter and the internal pointer WDP are initialized for a half cycle of low speed clock about 15 25us During the time period that they are initialized writing ...

Page 149: ... Description of Bits WDT2 0 bits 2 0 These bits are used to select an overflow period of the watchdog timer The WDT2 WDT1 and WDT0 bits set a overflow period TWOV of the WDT counter It is selectable from the following seven types of values WDT2 WDT1 WDT0 Description 0 0 0 125 ms 0 0 1 500 ms 0 1 0 2 s initial value 0 1 1 8 s 1 0 0 23 4 ms 1 0 1 31 25 ms 1 1 0 62 5ms 1 1 1 Prohibited Note When you ...

Page 150: ...system reset mode For the overflow period TWOV of the WDT counter it is selectable from the following seven types of values by the watchdog mode register WDTMOD Clear the WDT counter within the clear period of the WDT counter shown in Table 9 1 Table 9 1 Clear Period of WDT Counter WDT2 WDT1 WDT0 TWOV TWCL 0 0 0 125 ms Approx 121 ms 0 0 1 500 ms Approx 496 ms 0 1 0 2000 ms Approx 1996 ms 0 1 1 800...

Page 151: ...og timer interrupt request WDTINT is generated In this case the WDT counter and the internal pointer WDP are initialiaed for a half cycle of low speed clock about 15 26us If the WDT counter is not cleared even by the software processing performed following a watchdog timer interrupt and the WDT counter overflows again WDT reset occurs and the mode is shifted to a system reset mode Note In STOP mod...

Page 152: ...t released and the low speed clock LSCLK starts oscillating If the WDT counter gets overflow the WDT non maskable interrupt occurs and then a system reset occurs Therefore it is needed to clear the WDT counter even if you do not want to use the WDT See following example programming codes to clear the WDT counter in the interrupt routine Example programming code __DI Disable multi interrupts do WDT...

Page 153: ...Chapter 10 PWM ...

Page 154: ...MF2 is assigned to the fourthly function of the PB5 Port B or the tertiary function of the PC2 Port C For the functions of port A port B and port C see Chapter 15 Port A Chapter 16 Port B and Chapter 17 Port C 10 1 1 Features The PWM signals with the periods of approximately 122 ns PLLCLK 16 384MHz to 2s LSCLK 32 768kHz can be generated and output outside of the LSI The output logic of the PWM sig...

Page 155: ...nCON2 PWnCON3 R Cycle Matched Comparator HTBCLK Write PWnCL PnCK Write PWnCH Comparator Output control circuit PA0 PWMC PB0 PWMC PB7 PWMC PnNEG Duty Matched PnFLG 16 16 8 8 8 8 8 8 PWnPBUF PWnDBUF PWnPH L PWnDH L PWnCH latch Read PWnCL PLLCLK Emergency stop Control circuits PA1 PWMD PB1 PWMD PA2 PWME PB2 PWME External input PnTG PA0 to PA2 PB0 to PB7 CMP0 CMP1 TM9INT TMBINT TMFINT External input P...

Page 156: ...econdary function of the PB1 pin PB2 PnTG PWME I O External trigger input PWME output pin Used for the secondary function of the PB2 pin PB3 PnTG I External trigger input PB4 PnTG I External trigger input PB5 PnTG PWMF2 I O External trigger input PWMF2 output pin Used for the fourthly function of the PB5 pin PB6 PnTG PWMF1 I O External trigger input PWMF1 output pin Used for the fourthly function ...

Page 157: ...rol register 3 PWDCON3 R W 8 00H 0F930H PWME period register L PWEPL PWEP R W 8 16 0FFH 0F931H PWME period register H PWEPH R W 8 0FFH 0F932H PWME duty register L PWEDL PWED R W 8 16 00H 0F933H PWME duty register H PWEDH R W 8 00H 0F934H PWME counter register L PWECL PWEC R W 8 16 00H 0F935H PWME counter register H PWECH R W 8 00H 0F936H PWME control register 0 PWECON0 PWECON R W 8 16 00H 0F937H P...

Page 158: ...CP12 PCP11 PCP10 PCP9 PCP8 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 PWCPH and PWCPL are special function registers SFRs to set the PWMC periods Note When PWCPH or PWCPL is set to 0000H the PWMC period buffer PWCPBUF is set to 0001H The value written to PWCPH PWCPL during PWMC stop PCSTAT of PWCCON1 is 0 is transferred to PWCPBUF at the same time The value written to PWCPH ...

Page 159: ...2 PCD11 PCD10 PCD9 PCD8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PWCDH and PWCDL are special function registers SFRs to set the duties of PWMC Note Set PWCDH and PWCDL to values smaller than those to which PWCPH and PWCPL are set The value written to PWCDH PWCDL during PWMC stop PCSTAT of PWCCON1 is 0 is transferred to PWCDBUF at the same time The value written to PWCDH PW...

Page 160: ...meaningless Write data while the PWMC is stopped PCSTAT PCTGEN and PCRUN of PWCCON1 are 0 When data is read from PWCCL the value of PWCCH is latched When reading PWCCH and PWCCL use a word type instruction or pre read PWCCL The contents of PWCCH and PWCCL during PWM operation cannot be read depending on the combination of the PWM clock and system clock Table 10 1 shows PWCCH and PWCCL read enable ...

Page 161: ... 0 1 HTBCLK 1 0 PLLCLK 16 384MHz 1 1 Prohibited PCIS1 PCIS0 bits 3 2 The PCIS1 and PCIS0 bits are used to select the point at which the PWMC interrupt occurs When the periods match when the duties match or when the periods and duties match can be selected PCIS1 PCIS0 Description 0 0 When the periods matched initial value 0 1 When the duties matched 1 When the periods and duties matched PCNEG bit 4...

Page 162: ... the emergency stop by the external input initial value 1 Enables the count stop start and the emergency stop by the external input PCSDST bit 5 The PCSDST bit indicates that an emergency stop interrupt has occurred By writing 1 to the PCSDST the PCSDST becomes 0 PCSDST Description 0 An emergency stop interrupt has not occurred initial value 1 An emergency stop interrupt has occurred PCFLG bit 6 T...

Page 163: ... is set to 1 Set PCEXCL to 1 to clear the counter when stopped by the external input PCEXCL Description 0 Does not clear the counter when it is stopped by the external trigger initial value 1 Clears the counter when it is stopped by the external trigger PCTRM1 PCTRM0 bits 5 4 The PCTRM1 and PCTRM0 bits are used to select the count start stop mode of PWMC This is valid only when the external input ...

Page 164: ...1 0 0 CMP1 Comparator 1 PB4 pin 1 0 1 TM9INT Timer 9 interrupt PB5 pin 1 1 0 TMBINT Timer B interrupt PB6 pin 1 1 1 TMFINT Timer F interrupt PB7 pin Note When a timer interrupt request is set as the external trigger signal there are some restrictions on the edge selection of the PWM start stop triggers For details see the description of the PWCCON2 register The timer interrupt requests TM9INT TMBI...

Page 165: ...DP12 PDP11 PDP10 PDP9 PDP8 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 PWDPH and PWDPL are special function registers SFRs to set the PWMD periods Note When PWDPH or PWDPL is set to 0000H the PWMD period buffer PWDPBUF is set to 0001H The value written to PWDPH PWDPL during PWMD stop PDSTAT of PWDCON1 is 0 is transferred to PWDPBUF at the same time The value written to PWDPH ...

Page 166: ...12 PDD11 PDD10 PDD9 PDD8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PWDDH and PWDDL are special function registers SFRs to set the duties of PWMD Note Set PWDDH and PWDDL to values smaller than those to which PWDPH and PWDPL are set The value written to PWDDH PWDDL during PWMD stop PDSTAT of PWDCON1 is 0 is transferred to PWDDBUF at the same time The value written to PWDDH P...

Page 167: ... meaningless Write data while the PWM is stopped PDSTAT PDTGEN and PDRUN of PWDCON1 are 0 When data is read from PWDCL the value of PWDCH is latched When reading PWDCH and PWDCL use a word type instruction or pre read PWDCL The contents of PWDCH and PWDCL during PWM operation cannot be read depending on the combination of the PWM clock and system clock Table 10 2 shows PWDCH and PWDCL read enable ...

Page 168: ...l value 0 1 HTBCLK 1 0 PLLCLK 16 384MHz 1 1 Prohibited PDIS1 PDIS0 bits 3 2 The PDIS1 and PDIS0 bits are used to select the point at which the PWMD interrupt occurs When the periods match when the duties match or when the periods and duties match can be selected PDIS1 PDIS0 Description 0 0 When the periods matched initial value 0 1 When the duties matched 1 When the periods and duties matched PDNE...

Page 169: ...d the emergency stop by the external input Initial value 1 Enables the count stop start and the emergency stop by the external input PDSDST bit 5 The PDSDST bit indicates that an emergency stop interrupt has occurred By writing 1 to the PDSDST the PDSDST becomes 0 PDSDST Description 0 An emergency stop interrupt has not occurred initial value 1 An emergency stop interrupt has occurred PDFLG bit 6 ...

Page 170: ...ST1 is set to 1 Set PDEXCL to 1 to clear the counter when stopped by the external input PDEXCL Description 0 Does not clear the counter when it is stopped by the external trigger initial value 1 Clears the counter when it is stopped by the external trigger PDTRM1 PDTRM0 bits 5 4 The PDTRM1 and PDTRM0 bits are used to select the count start stop mode of PWMD This is valid only when the external inp...

Page 171: ...in 1 0 0 CMP1 Comparator 1 PB4 pin 1 0 1 TM9INT Timer 9 interrupt PB5 pin 1 1 0 TMBINT Timer B interrupt PB6 pin 1 1 1 TMFINT Timer F interrupt PB7 pin Note When a timer interrupt request is set as the external trigger signal there are some restrictions on the edge selection of the PWM start stop triggers For details see the description of the PWDCON2 register The timer interrupt requests TM9INT T...

Page 172: ...PEP12 PEP11 PEP10 PEP9 PEP8 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 PWEPH and PWEPL are special function registers SFRs to set the PWME periods Note When PWEPH or PWEPL is set to 0000H the PWME period buffer PWEPBUF is set to 0001H The value written to PWEPH PWEPL during PWME stop PESTAT of PWECON1 is 0 is transferred to PWEPBUF at the same time The value written to PWEPH...

Page 173: ...12 PED11 PED10 PED9 PED8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PWEDH and PWEDL are special function registers SFRs to set the duties of PWME Note Set PWEDH and PWEDL to values smaller than those to which PWEPH and PWEPL are set The value written to PWEDH PWEDL during PWME stop PESTAT of PWECON1 is 0 is transferred to PWEDBUF at the same time The value written to PWEDH P...

Page 174: ... meaningless Write data while the PWME is stopped PESTAT PETGEN and PERUN of PWECON1 are 0 When data is read from PWECL the value of PWECH is latched When reading PWECH and PWECL use a word type instruction or pre read PWECL The contents of PWECH and PWECL during PWM operation cannot be read depending on the combination of the PWM clock and system clock Table 10 3 shows PWECH and PWECL read enable...

Page 175: ...lue 0 1 HTBCLK 1 0 PLLCLK 16 384MHz 1 1 Prohibited PEIS1 PEIS0 bits 3 2 The PEIS1 and PEIS0 bits are used to select the point at which the PWME interrupt occurs When the periods match when the duties match or when the periods and duties match can be selected PEIS1 PEIS0 Description 0 0 When the periods matched Initial value 0 1 When the duties matched 1 When the periods and duties matched PENEG bi...

Page 176: ...d the emergency stop by the external input initial value 1 Enables the count stop start and the emergency stop by the external input PESDST bit 5 The PESDST bit indicates that an emergency stop interrupt has occurred By writing 1 to the PESDST the PESDST becomes 0 PESDST Description 0 An emergency stop interrupt has not occurred initial value 1 An emergency stop interrupt has occurred PEFLG bit 6 ...

Page 177: ...ST1 is set to 1 Set PEEXCL to 1 to clear the counter when stopped by the external input PEEXCL Description 0 Does not clear the counter when it is stopped by the external trigger initial value 1 Clears the counter when it is stopped by the external trigger PETRM1 PETRM0 bits 5 4 The PETRM1 and PETRM0 bits are used to select the count start stop mode of PWME This is valid only when the external inp...

Page 178: ...0 0 CMP1 Comparator 1 PB4 pin 1 0 1 TM9INT Timer 9 interrupt PB5 pin 1 1 0 TMBINT Timer B interrupt PB6 pin 1 1 1 TMFINT Timer F interrupt PB7 pin Note When a timer interrupt request is set as the external trigger signal there are some restrictions on the edge selection of the PWM start stop triggers For details see the description of the PWECON2 register The timer interrupt requests TM9INT TMBINT...

Page 179: ... PFP12 PFP11 PFP10 PFP9 PFP8 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 PWFPH and PWFPL are special function registers SFRs to set the PWMF0 to 2 periods The settable value is 0001H to FFFFH Note The value which wrote to PWFPH PWFPL during PWMF stop PFSTAT of PWFCON1 is 0 is transferred to PWFPBUF at the same time The value which wrote to PWFPH PWFPL during PWMF operation PF...

Page 180: ...12 PF0D11 PF0D10 PF0D9 PF0D8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PWF0DH and PWF0DL are special function registers SFRs to set the duties of PWMF0 Note Set PWF0DH and PWF0DL to values smaller than those to which PWFPH and PWFPL are set The value written to PWF0DH PWF0DL during PWMF stop PFSTAT of PWFCON1 is 0 is transferred to PWF0DBUF at the same time The value writte...

Page 181: ...12 PF1D11 PF1D10 PF1D9 PF1D8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PWF1DH and PW1FDL are special function registers SFRs to set the duties of PWMF1 Note Set PWF1DH and PWF1DL to values smaller than those to which PWFPH and PWFPL are set The value written to PWF1DH PWF1DL during PWMF stop PFSTAT of PWFCON1 is 0 is transferred to PWF1DBUF at the same time The value writte...

Page 182: ...12 PF2D11 PF2D10 PF2D9 PF2D8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PWF2DH and PWF2DL are special function registers SFRs to set the duties of PWMF2 Note Set PWF2DH and PWF2DL to values smaller than those to which PWFPH and PWFPL are set The value written to PWF2DH PWF2DL during PWMF stop PFSTAT of PWFCON1 is 0 is transferred to PWF2DBUF at the same time The value writte...

Page 183: ...aningless Write data while the PWM is stopped PFSTAT PFTGEN and PFRUN of PWFCON1 are 0 When data is read from PWFCL the value of PWFCH is latched When reading PWFCH and PWFCL use a word type instruction or pre read PWFCL The contents of PWFCH and PWFCL during PWMF0 to 2 operation cannot be read depending on the combination of the PWM clock and system clock Table 10 4 shows PWFCH and PWFCL read ena...

Page 184: ...3 2 The PFIS1 and PFIS0 bits are used to select the point at which the PWMF interrupt occurs When the periods match when the duties match or when the periods and duties match can be selected PFIS1 PFIS0 Description 0 0 When the periods matched initial value 0 1 When the duties matched 1 1 When the periods and duties matched 1 Select on which duty of PWMF0 to 2 an interrupt occurs using PWFCON5 PFD...

Page 185: ... emergency stop by the external input initial value 1 Enables the count stop start and the emergency stop by the external input PFSDST bit 5 The PFSDST bit indicates that an emergency stop interrupt of PWMF0 to 2 has occurred By writing 1 to the PFSDST the PFSDST becomes 0 PFSDST Description 0 An emergency stop interrupt has not occurred initial value 1 An emergency stop interrupt has occurred PFF...

Page 186: ... PFST1 is set to 1 Set PFEXCL to 1 to clear the counter when stopped by the external input PFEXCL Description 0 Does not clear the counter when it is stopped by the external trigger initial value 1 Clears the counter when it is stopped by the external trigger PFTRM1 PFTRM0 bits 5 4 The PFTRM1 and PFTRM0 bits are used to select the count start stop mode of PWMF0 to 2 This is valid only when the ext...

Page 187: ...B3 pin 1 0 0 CMP1 Comparator 1 PB4 pin 1 0 1 TM9INT Timer 9 interrupt PB5 pin 1 1 0 TMBINT Timer B interrupt PB6 pin 1 1 1 TMFINT Timer F interrupt PB7 pin Note When a timer interrupt request is set as the external trigger signal there are some restrictions on the edge selection of the PWM start stop triggers For details see the description of the PWFCON2 register The timer interrupt requests TM9I...

Page 188: ...FSTAT PFTGEN and PFRUN of the PWFCON1 are 0 Description of Bits PF2POL PF1POL PF0POL bits 2 to 0 The PF2POL PF1POL and PF0POL bits are used to select the output polarity of PWMF0 to 2 PFnPOL Description 0 Output the polarity set by PFNEG of PWFCON0 Initial value 1 Output the reverse of the polarity set by PFNEG of PWFCON0 n 2 to 0 PF2EN PF1EN PF0EN bits 6 to 4 The PF2EN PF1EN and PF0EN are output ...

Page 189: ... 0 The period register and the duty register are not updated during operation initial value 1 The period register and the duty register are updated during operation Note If you write 1 to PFUD to update register value do so after reading PFUD and confirm that the value is 0 update is completed PFDISL1 PFDISL0 bit 3 to 2 The PFDISL1 and PFDISL0 bits are used to select PWM output which generates an ...

Page 190: ...registers stop counting after counting once the falling of the PWMn clock PnCK To confirm that PWnCH and PWnCL are stopped check that the PnSTAT bit of the PWMn control register 1 PWnCON1 is 0 When the PnRUN bit is set to 1 again the PWnCH and PWnCL counter registers restarts incremental counting from the previous value on the falling edge of PnCK To initialize the PWnCH and PWnCL counter register...

Page 191: ...s up to the falling edge the PWMn status flag PnSTAT is in a 1 state of the next PWMn clock pulse Therefore the PWMn interrupt PWnINT may occur An external triggering stop becomes invalid after setting a PnRUN bit during a PWM stop 1 until PnSTAT is set to 1 Moreover an external triggering start becomes invalid after making a PnRUN bit a PWM busy 0 until PnSTAT is set to 0 PWnCH L XXXX 0000 8000 P...

Page 192: ...the external input Figure 10 3 Timing Diagram of sampling of the external input 10 3 2 Emergency Stop Operation Setting the PnSDE1 and PnSDE0 bits of the PWMn control register 3 PWnCON3 enables the emergency stop function with the selected external input When the selected external input gets a rising edge input the emergency stop flag PnSDST is set to 1 an emergency stop interrupt PWnINT is genera...

Page 193: ...es Polarity of each wave form can be set individually by the combination of PFNEG and PFnPOL PFNEG PFnPOL PWFn initial value 0 0 0 0 1 1 1 0 1 1 1 0 The following shows a PWM waveform when PFNEG 1 PF2POL 0 PF1POL 1 and PF0POL 0 PWFC PWFD0BUF PWFD1BUF PWFD2BUF PFRUN PWF0 PWF1 PWF2 PFNEG PWFPBUF PF0POL PF1POL PF2POL PF0FLG PF1FLG PF2FLG Figure 10 5 PWMF Operation Example ...

Page 194: ...on confirm that PFUD bit of PWFCON5 is 0 and then write 1 to it after setting as desired Figure 10 6 Update Timing Diagram During PWMF Operation 1 Each buffer is updated at set timing during operation stopped 2 Each buffer is updated at the beginning of the next period where PFUD is set to 1 during operation 1 2 PFRUN PWFC PF0FLG PF1FLG PF2FLG PWFP PWFD0 PWFD1 PWFD2 PFUD PWFPBUF PWFD2BUF PWFD1BUF ...

Page 195: ...mode 1 In some settings such as when the set period is short and when the PWM clock is selected where PWnC cannot be read interrupts cannot be identified 2 They can be identified only when PnEXCL bit of the PWnCON2 register is set to 0 Figure 10 7 Identifying PWM Interrupt Read PnRUN bit When continuous mode is selected PnRUN 0 PnRUN 1 Read PWnC register 1 PWnC PWnD PWnC PWnD Count stop interrupt ...

Page 196: ... PA1MD1 PA0MD1 Data 0 Reg name PAMOD0 register Address 0F254H Bit 7 6 5 4 3 2 1 0 Bit name PA2MD0 PA1MD0 PA0MD0 Data 1 Set PA0C1 bit bit0 of PACON1 register to 1 and set PA0C0 bit bit0 of PACON0 register to 1 for specifying the PA0 as CMOS output Reg name PACON1 register Address 0F253H Bit 7 6 5 4 3 2 1 0 Bit name PA2C1 PA1C1 PA0C1 Data 1 Reg name PACON0 register Address 0F252H Bit 7 6 5 4 3 2 1 0...

Page 197: ... of PBCON0 register to 1 and set PB0DIR bit bit0 of PBDIR register to 0 for specifying the PB0 as CMOS output Reg name PBCON1 register Address 0F23BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 P35C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1 Data 1 Reg name PBCON0 register Address 0F23AH Bit 7 6 5 4 3 2 1 0 Bit name PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0 Data 1 Reg name PBDIR register Address 0F239H Bit...

Page 198: ...of PBCON0 register to 1 and set PB7DIR bit bit7 of PBDIR register to 0 for specifying the PB7 as CMOS output Reg name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 P35C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1 Data 1 Reg name PBCON0 register Address 0F25AH Bit 7 6 5 4 3 2 1 0 Bit name PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0 Data 1 Reg name PBDIR register Address 0F259H Bit ...

Page 199: ...Chapter 11 Synchronous Serial Port ...

Page 200: ...ster or slave selectable MSB first or LSB first selectable 8 bit length or 16 bit length selectable for the data length 11 1 2 Configuration Figure 11 1 shows the configuration of the synchronous serial port SIO0BUFL Serial port transmit receive buffer L SIO0BUFH Serial port transmit receive buffer H SIO0CON Serial port control register SIO0MOD0 Serial port mode register 0 SIO0MOD1 Serial port mod...

Page 201: ...1 1 3 List of Pins Pin name I O Description PB3 SIN I Receive data input Used for the secondary function of the PB3 pin PB5 SCK I O Synchronous clock input output Used for the secondary function of the PB5 pin PB4 SOUT O Transmit data output Used for the secondary function of the PB4 pin ...

Page 202: ... Byte Symbol Word R W Size Initial value 0F280H Serial port 0 transmit receive buffer L SIO0BUFL SIO0BUF R W 8 16 00H 0F281H Serial port 0 transmit receive buffer H SIO0BUFH R W 8 00H 0F282H Serial port 0 control register SIO0CON R W 8 00H 0F284H Serial port 0 mode register 0 SIO0MOD0 SIO0MOD R W 8 16 00H 0F285H Serial port 0 mode register 1 SIO0MOD1 R W 8 00H ...

Page 203: ...s 0F281H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SIO0BUFH S0B15 S0B14 S0B13 S0B12 S0B11 S0B10 S0B9 S0B8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 SIO0BUFL and SIO0BUFH are special function registers SFRs to write transmit data and to read receive data of the synchronous serial port When data is written in SIO0BUFL and SIO0BUFH the data is written in ...

Page 204: ...0 0 0 0 SIO0CON is a special function register SFR to control the synchronous serial port Description of Bits S0EN bit 0 The S0EN bit is used to specify start of synchronous serial communication Writing a 1 to this bit starts 8 16 bit data communication This bit is set to 0 automatically when 8 16 bit data communication is terminated The S0EN bit is set to 0 at a system reset S0EN Description 0 St...

Page 205: ...0MD1 S0MD0 bits 2 1 The S0MD1 and S0MD0 bits are used to select transmit receive or transmit receive mode of the synchronous serial port S0MD1 S0MD0 Description 0 0 Stops transmission reception initial value 0 1 Receive mode 1 0 Transmit mode 1 1 Transmit receive mode S0LG bit 3 The S0LG bit is used to specify the bit length of the transmit receive buffer 8 bit or 16 bit length The S0LG bit is set...

Page 206: ... 0 1 1 1 8 HSCLK 0 1 0 0 1 16 HSCLK 0 1 0 1 1 32 HSCLK 0 1 1 0 External clock 0 PB5 SCK 0 1 1 1 Prohibited 1 0 Prohibited 1 1 0 0 1 1 HSCLK 1 1 0 1 1 2 HSCLK 1 1 1 Prohibited Note In slave mode the maximum input frequency of the SCK is 2MHz In master mode the maximum output frequency of the SCK is 4 2MHz If you select the 1 1 HSCLK S0CK3 0 is set to 1100b you must set the HSCLK less than 4 2MHz Fo...

Page 207: ...ck is selected in the serial port mode register SIO0MOD1 the LSI is set to a master mode and when an external clock PB5 SCK is selected the LSI is set to a slave mode The serial port mode register SIO0MOD0 enables selection of MSB first LSB first The transmit data output pin PB4 SOUT and transfer clock input output pin PB5 SCK must be set to the secondary functions Figures 11 2 and 11 3 show the t...

Page 208: ...a slave mode The serial port mode register SIO0MOD0 enables selection of MSB first or LSB first The receive data input pin PB3 SIN and transfer clock input output pin PB5 SCK must be set to the secondary function Figures 11 4 and 11 5 show the receive operation waveforms of the synchronous serial ports for clock type 0 and clock type 1 respectively 8 bit length MSB first clock types 0 and 1 Figure...

Page 209: ...n pins PB4 SOUT of GPIO When an internal clock is selected in the serial port mode register SIO0MD1 the LSI is set to a master mode and when an external clock PB5 SCK is selected the LSI is set ot a slave mode The serial port mode register SIO0MOD0 enables selection of MSB first or LSB first The receive data input pin PB3 SIN the transmit data output pin PB4 SOUT and transfer clock input output pi...

Page 210: ...4C1 bit PBCON1 register bit5 4 to 1 setting PB5C0 PB4C0 bit PBCON0 register bit5 4 to 1 and setting PB5DIR PB4DIR bit PBDIR register bit5 4 to 0 Additionally the PB3 pin is selected as input pin by setting PB3DIR bit PBDIR register bit3 to 1 The setting value of PB3C1 bit and PB3C0 bit is optional Optional states are selected according to the state of the external circuit where the PB3 pin is conn...

Page 211: ...1 and setting PB4DIR bit PBDIR register bit4 to 0 Additionally the PB5 and PB3 pin is selected as input pin by setting PB5DIR PB3DIR bit PBDIR register bit5 3 to 1 The setting value of PB5C1 PB3C1 bit and PB5C0 PB3C0 bit is optional Optional input modes are selected according to the state of the external circuit where the PB5 and PB3 pin is connected reg name PBCON1 register Address 0F25BH bit 7 6...

Page 212: ...Chapter 12 UART ...

Page 213: ...rity error flag overrun error flag framing error flag and transmit buffer status flag Positive logic or negative logic selectable as communication logic LSB first or MSB first selectable as a communication direction Communication speed Settable within the range of 2400bps to 115200bps Built in baud rate generator 12 1 2 Configuration Figure 12 1 shows the configuration of the UART UAnBUF UARTn tra...

Page 214: ...function of the PB3 pin 12 2 Description of Registers 12 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F290H UART0 transmit receive buffer UA0BUF R W 8 00H 0F291H UART0 control register UA0CON R W 8 00H 0F292H UART0 mode register 0 UA0MOD0 UA0MOD R W 8 16 00H 0F293H UART0 mode register 1 UA0MOD1 R W 8 00H 0F294H UART0 baud rate register L UA0BRTL UA0BRT R W 8 1...

Page 215: ...Note For operation in transmit mode be sure to set the transmit mode UA0MOD0 and UA0MOD1 before setting the transmitted data in UA0BUF 12 2 3 UART1 Transmit Receive Buffer UA1BUF Address 0F298H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 UA1BUF U1B7 U1B6 U1B5 U1B4 U1B3 U1B2 U1B1 U1B0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 UA1BUF is a special function ...

Page 216: ...tinued To terminate reception set the bit to 0 by software U0EN Description 0 Stops communication Initial value 1 Starts communication 12 2 5 UART1 Control Register UA1CON Address 0F299H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 UA1CON U1EN R W R W Initial value 0 0 0 0 0 0 0 0 UA1CON is a special function register SFR to control start stop communication of the UART Descripti...

Page 217: ...U0CK1 U0CK0 bits 2 1 The U0CK1 and U0CK0 bits are used to select the clock to be input to the baud rate generator of the UART0 U0CK1 U0CK0 Description 0 0 LSCLK initial value 0 1 Prohibited 1 HSCLK U0RSEL bit 4 The U0RSEL bit is used to select the received data input pin for the UART0 U0RSEL Description 0 Selects the PB0 pin Initial value 1 Selects the PB5 pin U0RSS bit 5 The U0RSS bit is used to ...

Page 218: ...U1CK1 U1CK0 bits 2 1 The U1CK1 and U1CK0 bits are used to select the clock to be input to the baud rate generator of the UART1 U1CK1 U1CK0 Description 0 0 LSCLK initial value 0 1 Prohibited 1 HSCLK U1RSEL bit 4 The U1RSEL bit is used to select the received data input pin for the UART1 U1RSEL Description 0 Selects the PB2 pin Initial value 1 Selects the PB7 pin U1RSS bit 5 The U1RSS bit is used to ...

Page 219: ...h U0PT1 U0PT0 bits 3 2 The U0PT1 and U0PT0 bits are used to select even parity odd parity or no parity in the communication of the UART U0PT1 U0PT0 Description 0 0 Even parity initial value 0 1 Odd parity 1 No parity bit U0STP bit 4 The U0STP bit is used to select the stop bit length in the communication of the UART U0STP Description 0 1 stop bit initial value 1 2 stop bits U0NEG bit 5 The U0NEG b...

Page 220: ...h U1PT1 U1PT0 bits 3 2 The U1PT1 and U0PT0 bits are used to select even parity odd parity or no parity in the communication of the UART U1PT1 U1PT0 Description 0 0 Even parity initial value 0 1 Odd parity 1 No parity bit U1STP bit 4 The U1STP bit is used to select the stop bit length in the communication of the UART U1STP Description 0 1 stop bit initial value 1 2 stop bits U1NEG bit 5 The U1NEG b...

Page 221: ... 0F295H Access R W Access size 8 bit Initial value 0FH 7 6 5 4 3 2 1 0 UA0BRTH U0BR11 U0BR10 U0BR9 U0BR8 R W R W R W R W R W Initial value 0 0 0 0 1 1 1 1 UA0BRTL and UA0BRTH are special function registers SFRs to set the count value of the baud rate generator which generates baud rate clocks For the relationship between the count value of the baud rate generator and baud rate see Section 12 3 2 B...

Page 222: ... 0F29DH Access R W Access size 8 bits Initial value 0FH 7 6 5 4 3 2 1 0 UA1BRTH U1BR11 U1BR10 U1BR9 U1BR8 R W R W R W R W R W Initial value 0 0 0 0 1 1 1 1 UA1BRTL and UA1BRTH are special function registers SFRs to set the count value of the baud rate generator which generates baud rate clocks For the relationship between the count value of the baud rate generator and baud rate see Section 12 3 2 ...

Page 223: ...N bit and then reception is restarted this bit is set to 1 if the previously received data is not read Therefore make sure that data is always read from the transmit receive buffer even if the data is not required The U0OER bit is fixed to 0 in transmit mode U0OER Description 0 No overrun error initial value 1 Overrun error U0PER bit 2 The U0PER bit is used to indicate occurrence of a parity error...

Page 224: ...N bit and then reception is restarted this bit is set to 1 if the previously received data is not read Therefore make sure that data is always read from the transmit receive buffer even if the data is not required The U1OER bit is fixed to 0 in transmit mode U1OER Description 0 No overrun error initial value 1 Overrun error U1PER bit 2 The U1PER bit is used to indicate occurrence of a parity error...

Page 225: ...All these options are set with the UARTn mode register 1 UAnMOD1 Figure 12 2 and Figure 12 3 show the positive logic input output format and negative logic input output format respectively Figure 12 2 Positive Logic Input Output Format Figure 12 3 Negative Logic Input Output Format Start bit 1 2 3 4 5 6 7 8 Parity bit Data bit 1 frame 1 frame Max 12 bits Min 7 bits Data bit length 8 to 5 bits vari...

Page 226: ...UAnBRTL are expressed by the following equation UAnBRTH L Clock frequency Hz 1 Baud rate bps Table 12 1 lists the count values for typical baud rates Table 12 1 Count Values for Typical Baud Rates Baud rate Baud rate generator Clock selection Baud rate generator counter value Error Baud rate Clock Count value Period of one bit UAnBRTH UAnBRTL 2400bps 8 192MHz 3413 Approximately 417us 0DH 054H 0 01...

Page 227: ...he TXDn output U0B6 U0B3 U0B7 U0B5 U0B2 U0B1 U0B4 U0B0 LSB transmission LSB reception Data length 8 bits Data length 7 bits Data length 6 bits U0B7 is 0 at completion of reception Data length 5 bits MSB reception MSB transmission U0B6 U0B3 U0B5 U0B2 U0B1 U0B4 U0B0 LSB transmission LSB reception MSB reception MSB transmission U0B7 and U0B6 are 0 at completion of reception U0B3 U0B5 U0B2 U0B1 U0B4 U...

Page 228: ...to be transmitted is written to the transmit receive buffer UAnBUF the transmit buffer status flag UnFUL is set to 1 and a UARTn interrupt is requested on the falling edge of the internal transfer clock after transmission of the stop bit If the UARTn interrupt routine is terminated without writing the next data to the transmit receive buffer the UnFUL bit is not set to 1 and transmission continues...

Page 229: ...top bit error and a parity bit error When an error is detected the LSI sets the corresponding bit of the UARTn status register UAnSTAT to 1 Parity error SnPER 1 Overrun error SnOER 1 Framing error SnFER 1 The rise of the internal transfer clock is set so that it may fall into the middle of the bit interval of the received data Reception continues until the UnEN bit is reset to 0 by the program Whe...

Page 230: ...the baud rate and shifted into the shift register This sampling timing where the receive data is sampled to be shifted into the shift register can be adjusted by one clock pulse of the baud rate generator clock by using the UnRSS bit of the UARTn mode register 0 UAnMOD0 Figure 12 8 shows the relationship between the UnRSS bit and sampling timing 1 When the baud rate generator count value is 7 odd ...

Page 231: ...2 9 shows the waveform indicating baud rate errors and reception margin Figure 12 9 Baud Rate Errors and Reception Margin Note When doing system design ensure enough reception margin taking into account the effects of noise and receive data rounding as well as the difference in baud rate between the transmitter side and receiver side and a delay in the detection of start bit When the baud rate on ...

Page 232: ...he PB1C0 bit bit1 of PBCON0 register to 1 and the PB1DIR bit bit1 of PBDIR register to 0 for specifying the state mode of the PB1 pin to CMOS output Set the PB0DIR bit bit0 of PBDIR register to 1 for specifying the PB0 as an input pin The set value is arbitrary for the PB0C1 and PB0C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB0 pin is connect...

Page 233: ...s arbitrary for the PB5C1 and PB5C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB5 pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1 Setting value 1 Register name PBCON0 register Address 0F25AH Bit 7 6 5 4 3 2 1 0 Bit name PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0...

Page 234: ...IR register to 0 for specifying the state mode of the PB1 pin to CMOS output Set the PB2DIR bit bit2 of PBDIR register to 1 for specifying the PB2 as an input pin The set value is arbitrary for the PB2C1 and PB2C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB2 pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit ...

Page 235: ...or specifying the state mode of the PB3 pin to CMOS output Set the PB2DIR bit bit2 of PBDIR register to 1 for specifying the PB2 as an input pin The set value is arbitrary for the PB2C1 and PB2C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB2pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB...

Page 236: ...register to 0 for specifying the state mode of the PB4 pin to CMOS output Set the PB2DIR bit bit2 of PBDIR register to 1 for specifying the PB2 as an input pin The set value is arbitrary for the PB2C1 and PB2C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB2 pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit nam...

Page 237: ... register to 0 for specifying the state mode of the PB1 pin to CMOS output Set the PB7DIR bit bit7 of PBDIR register to 1 for specifying the PB7 as an input pin The set value is arbitrary for the PB7C1 and PB7C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB7pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit nam...

Page 238: ...r specifying the state mode of the PB3 pin to CMOS output Set the PB7DIR bit bit7 of PBDIR register to 1 for specifying the PB7 as an input pin The set value is arbitrary for the PB7C1 and PB7C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB7 pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB...

Page 239: ...n The set value is arbitrary for the PB7C1 and PB7C0 bits Select an arbitrary input mode depending on the state of the external circuit to which the PB7pin is connected Register name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1 Setting value 1 Register name PBCON0 register Address 0F25AH Bit 7 6 5 4 3 2 1 0 Bit name PB7C0 PB6C0 PB5C0 P...

Page 240: ...Chapter 13 I2 C Bus Interface Master ...

Page 241: ...iguration of the I2 C bus interface I2C0RD I 2 C bus 0 receive register I2C0SA I 2 C bus 0 slave address register I2C0TD I 2 C bus 0 transmit data register I2C0CON I 2 C bus 0 control register I2C0MOD I 2 C bus 0 mode register I2C0STAT I 2 C bus 0 status register Figure 13 1 Configuration of I 2 C Bus Interface 13 1 3 List of Pins Pin name I O Description PB6 SDA I O I 2 C bus interface data input...

Page 242: ...bol Byte Symbol Word R W Size Initial value 0F2A0H I 2 C bus 0 receive register I2C0RD R 8 00H 0F2A1H I 2 C bus 0 slave address register I2C0SA R W 8 00H 0F2A2H I 2 C bus 0 transmit data register I2C0TD R W 8 00H 0F2A3H I 2 C bus 0 control register I2C0CON R W 8 00H 0F2A4H I 2 C bus 0 mode register I2C0MOD R W 8 00H 0F2A5H I 2 C bus 0 status register I2C0STAT R 8 00H ...

Page 243: ...C0RD is updated after completion of each reception Description of Bits I20R7 I20R0 bits 7 to 0 The I20R7 to I20R0 bits are used to store receive data The signal input to the SDA pin is received at transmission of a slave address and at data transmission reception in sync with the rising edge of the signal on the SCL pin Since the signal of the SDA pin sync with the rising edge of the signal of the...

Page 244: ... W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2C0SA is a special function register SFR to set the address and the data direction bit of the slave device Description of Bits I20RW bit 0 The I20RW bit is a data direction bit It used to select the data transmit mode write or data receive mode read I20RW Description 0 Data transmit mode initial value 1 Data receive mode I20A6 I20A0 bits 7 to 1...

Page 245: ... 0F2A2H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 I2C0TD I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2C0TD is a special function register SFR to set transmit data Description of Bits I20T7 0 bits 7 to 0 The I20T7 to 0 bits are used to set transmit data ...

Page 246: ... I20EN 1 When the I20SP bit is set to 1 the I20ST bit is set to 0 I20ST Description 0 Stops communication initial value 1 Starts communication I20SP bit 1 The I20SP bit is a write only bit used to request a stop condition When the I20SP bit is set to 1 the I2 C bus shifts to the stop condition and communication stops When the I20SP bit is read 0 is always read I20SP Description 0 No stop condition...

Page 247: ...ce Standard mode or fast mode can be selected I20MD Description 0 Standard mode initial value 100kbps 8MHz HSCLK 1 Fast mode 400kbps 8MHz HSCLK I20DW1 I20DW0 bits 3 2 The I20DW1 and I20DW0 bits are used to set the communication speed reduction rate of the I2 C bus interface Set this bit so that the communication speed does not exceed 100kpbs 400kpbs I20DW1 I20DW0 Description 0 0 No communication s...

Page 248: ...0 I 2 C bus free state Initial value 1 I 2 C bus busy state I20ACR bit 1 The I20ACR bit is used to store the acknowledgment signal received Acknowledgment signals are received each time the slave address is received and data transmission or reception is completed The I20ACR bit is set to 0 when the I20EN bit of I2C0MOD is 0 I20ACR Description 0 Receives acknowledgment 0 Initial value 1 Receives ac...

Page 249: ... I2C0TD is transmitted in MSB first and finally the acknowledgment signal is received in the I20ACR bit of the I2 C bus 0 status register I2CSTAT At completion of acknowledgment reception the LSI shifts to the I2 C bus 0 control register I2C0CON setting wait state control register setting wait state The value of I2C0TD output from the SDA pin is stored in I2C0RD 13 3 1 5 Data Receive Mode In data ...

Page 250: ...D 0 D 7 A Receive data Value of I2C0SA S r S P S r Transmission Reception Start condition Stop condition Repeated start condition Reception of acknowledgment Transmission of acknowledgment Transmission of non acknowledgment A A A I20CSA xxxxxxx0B I2C0CON 01H I2C0TD xxH I2C0CON 01H I2C0TD xxH I2C0CON 01H I2C0TD xxH I2C0CON 01H Value of I2C0TD S A 6 A 5 A 4 A 3 A 2 A 1 A 0 R W A D 6 D 0 D 7 A D 6 D ...

Page 251: ... output until termination of the subsequent byte data communication I20ER bit is initialized to 0 by writing in any value to I2 C bus 0 control register I2C0CON Figure 13 6 shows the operation timing and control method when transmission fails Figure 13 6 Operation Timing When Transmission Fails I2C0SA xxxxxxx0B I2C0CON 01H S A 6 A 5 A 4 A 3 A 2 A 1 A 0 R W A P I2C0CON 02H Value of I2C0SA Value of ...

Page 252: ... reduction 88φ 40φ 48φ 8φ 40φ 48φ 40φ 40φ 48φ 20 reduction 96φ 44φ 52φ 8φ 44φ 52φ 44φ 44φ 52φ 30 reduction 104φ 48φ 56φ 8φ 48φ 56φ 48φ 48φ 56φ Fast mode 400 kbps No reduction 20φ 8φ 12φ 4φ 8φ 12φ 8φ 8φ 12φ 10 reduction 22φ 8φ 14φ 4φ 8φ 14φ 10φ 8φ 14φ 20 reduction 24φ 10φ 14φ 4φ 10φ 14φ 10φ 10φ 14φ 30 reduction 26φ 10φ 16φ 4φ 10φ 16φ 12φ 10φ 16φ φ Period of high speed clock HSCLK Note The HSCLK clo...

Page 253: ... bit bit6 5 of PBCON1 register to 1 set PB6C0 PB5C0 bit bit6 5 of PBCON0 register to 0 and set PB6DIR PB5DIR bit bit6 5 of PBDIR register to 0 for specifying the PB6 and PB5 as Nch open drain output The open drain open collector outputs are required on the I2C bus line to avoid collision between H level and L level Reg name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name PB7C1 PB6C1 PB...

Page 254: ...Chapter 14 I2 C Bus Interface Slave ...

Page 255: ...supported include standard mode 100 kbps Support for clock synchronization handshake Note Not supported for fast mode 400kbps of communication speed and 10 bit address 14 1 2 Configuration Figure 14 1 shows the configuration of the I2 C bus interface I2C1RD I 2 C bus 1 receive register I2C1SA I 2 C bus 1 slave address register I2C1TD I 2 C bus 1 transmit data register I2C1CON I 2 C bus 1 control r...

Page 256: ... tertiary function of the PB6 pin PB5 SCL I O I 2 C bus interface clock input output pin Used for the tertiary function of the PB5 pin PC5 SDA I O I 2 C bus interface clock input output pin Used for the secondary function of the PC5 pin PC4 SCL I O I 2 C bus interface clock input output pin Used for the secondary function of the PC4 pin Note The PC5 SDA and PC4 SCL pins are only used by ML610Q112 ...

Page 257: ...yte Symbol Word R W Size Initial value 0F2A8H I 2 C bus 1 receive register I2C1RD R 8 00H 0F2A9H I 2 C bus 1 slave address register I2C1SA R W 8 00H 0F2AAH I 2 C bus 1 transmit data register I2C1TD R W 8 00H 0F2ABH I 2 C bus 1 control register I2C1CON R W 8 00H 0F2ACH I 2 C bus 1 mode register I2C1MOD R W 8 00H 0F2ADH I 2 C bus 1 status register I2C1STAT R 8 00H ...

Page 258: ...receive data I2C1RD is updated after completion of each reception Description of Bits I21R7 I21R0 bits 7 to 0 The I21R7 to I21R0 bits are used to store receive data The signal input to the SDA pin is received at transmission of a slave address and at data transmission reception in sync with the rising edge of the signal on the SCL pin Since data that has been output to the SDA and SCL pins is rece...

Page 259: ...ccess size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 I2C1SA I21A6 I21A5 I21A4 I21A3 I21A2 I21A1 I21A0 R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2C1SA is a special function register SFR to set the slave address Description of Bits I21A6 I21A0 bits 7 to 1 The I21A6 to I21A0 bits are used to set the slave address of the communication destination ...

Page 260: ...AAH Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 I2C1TD I21T7 I21T6 I21T5 I21T4 I21T3 I21T2 I21T1 I21T0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2C1TD is a special function register SFR to set transmit data Description of Bits I21T7 I21T0 bits 7 to 0 The I21T7 to I21T0 bits are used to set transmit data ...

Page 261: ...perations Description of Bits I21WT bit 5 The I21WT bit is a write only bit used to cancel the waiting status for communication output L level to SCL pin When this bit is set to 1 during the waiting status for communication it cancel the waiting status This bit always returns 0 for read I21WT Description 0 Do not cancel the wait initial value 1 Cancel the wait I21ACT bit 7 The I21ACT bit is used t...

Page 262: ...set to 1 it enables the operation of I2 C bus 1 When the I21EN bit is set to 0 all bits of I2 C bus 1 status register I2C1STAT is initialized by 0 and I2 C bus 1 stop the operation I21EN Description 0 Stops I 2 C operation Initial value 1 Enables I 2 C operation I21PIE bit 5 The I21PIE bit is used to select enable or disable the stop condition interrupt I21PIE Description 0 Disables the stop condi...

Page 263: ...ion or reception is completed The I21ACR bit is set to 0 when the I21EN bit of I2C1MOD is 0 I21ACR Description 0 Receives acknowledgment 0 Initial value 1 Receives acknowledgment 1 I21ER bit 2 The I21ER bit is used to indicate a transmit error When the value of the bit transmitted and the value of the SDA pin do not coincide this bit is set to 1 When the I21ER bit is set to 1 the SDA pin output is...

Page 264: ...bit indicates status of transmission and receive The I21TR bit is set to 1 when detecting data direction bit is 1 The I21TR bit is reset to 0 when detecting stop condition start condition data direction bit is 0 and when I21EN bit of I2C1MOD0 is 0 I21TR Description 0 Receive state initial value 1 Transmit state ...

Page 265: ...preparation for the next data is completed it cancel the communication wait state by setting the I21WT bit of I2C1CON register In data transmit mode after setting the next data to I2C1RD register the I21WT bit is set to 1 and cancel the communication wait state 14 3 1 4 Data Transmit Mode In data transmit mode the value of I2C1TD is transmitted in MSB first and finally the acknowledgment signal is...

Page 266: ...D 6 D 0 D 7 A Transmit data Slave address S r I2C1TD xxH I2C1CON 20H I2C1TD xxH I2C1CON 20H I2C1TD xxH I2C1CON 20H Transmit data S A 6 A 5 A 4 A 3 A 2 A 1 A 0 R W A D 6 D 0 D 7 A D 6 D 7 D 0 A D 6 D 7 D 0 A P I2C1CON 20H Transmit data Transmit data Slave address Slave address Transmit data Transmit data Transmit data Register setting SDA I2CSINT I21SAA I2C1RD I21TR S P S r Reception Start conditio...

Page 267: ...I2C1CON Figure 14 5 shows the operation timing and control method when transmission fails Figure 14 5 Operation Timing When Transmission Fails 14 3 3 Operation Waveforms Figure 14 6 shows the operation waveforms of the SDA and SCL signals and the I21BB flag Figure 14 6 Operation Waveforms of SDA and SCL Signals and I21BB Flag I2C1TD xxH I2C1CON 20H D 6 D 5 D 4 D 3 I2C1CON 00H Undefined data Regist...

Page 268: ...t PB6C1 PB5C1 bit bit6 5 of PBCON1 register to 1 set PB6C0 PB5C0 bit bit6 5 of PBCON0 register to 0 and set PB6DIR PB5DIR bit bit6 5 of PBDIR register to 0 for specifying the PB6 and PB5 as Nch open drain output The open drain open collector outputs are required on the I2C bus line to avoid collision between H level and L level Reg name PBCON1 register Address 0F25BH Bit 7 6 5 4 3 2 1 0 Bit name P...

Page 269: ...Chapter 15 Port A ...

Page 270: ...ation Type A D Converter for the external clock and output of clock see Chapter 6 Clock Generation Circuit for the Timers see Chapter 8 Timers 15 1 1 Features Allows selection of high impedance output P channel open drain output N channel open drain output or CMOS output for each bit in output mode Allows selection of high impedance input input with a pull down resistor or input with a pull up res...

Page 271: ...register 0 PACON1 Port A control register 1 PAMOD0 Port A mode register 0 PAMOD1 Port A mode register 1 Figure 15 1 Configuration of Port A 3 CMP1P AIN0 AIN1 PWMC PWMD PWME CMP0OUT OUTCLK LSCLK TM9OUT TMFOUT 3 Trigger Inputs TETG TFTG PCTG PDTG PETG PFTG Data bus PA0 to PA2 PADIR PAMOD0 1 PACON0 1 VDD VDD VSS VSS 8 PortA Output Controller PAD VDD VSS Pull up Pull down Controller CLKIN Trigger Inpu...

Page 272: ...DC 1 input Analog comparator 1 inverted input Timer n trigger input PWM m trigger input PWMD output Low speed clock output LSCLK Timer F out TMFOUT PA2 EXI2 TnTG PmTG I O Input output port External 2 interrupt Timer n trigger input PWM m trigger input PWME output External clock input CLKIN Comparator 0 output CMP0OUT n E F m C D E F Note PA0 and PA1 are assigned to the input of SA ADC When used as...

Page 273: ...l Byte Symbol Word R W Size Initial value 0F250H Port A data register PAD R W 8 00H 0F251H Port A direction register PADIR R W 8 00H 0F252H Port A control register 0 PACON0 PACON R W 8 16 00H 0F253H Port A control register 1 PACON1 R W 8 00H 0F254H Port A mode register 0 PAMOD0 PAMOD R W 8 16 00H 0F255H Port A mode register 1 PAMOD1 R W 8 00H ...

Page 274: ...irection register PADIR described later Description of Bits PA2D PA0D bits 2 to 0 The PA2D to PA0D bits are used to set the output value of the Port A pin in output mode and to read the pin level of the Port A pin in input mode PA0D Description 0 Output or input level of the PA0 pin L 1 Output or input level of the PA0 pin H PA1D Description 0 Output or input level of the PA1 pin L 1 Output or inp...

Page 275: ...l value 0 0 0 0 0 0 0 0 PADIR is a special function register SFR to select the input output mode of Port A Description of Bits PA2DIR PA0DIR bits 2 to 0 The PA2DIR to PA0DIR pins are used to set the input output direction of the Port A pin PA0DIR Description 0 PA0 pin Output initial value 1 PA0 pin Input PA1DIR Description 0 PA1 pin Output initial value 1 PA1 pin Input PA2DIR Description 0 PA2 pin...

Page 276: ...l up resistor in input mode High impedance output means the status that both of H level output and L level output turn off Setting of PA0 pin When output mode is selected PA0DIR bit 0 When input mode is selected PA0DIR bit 1 PA0C1 PA0C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down resistor 1 0 N channel open drain o...

Page 277: ... are used to select the primary secondary tertiary and fourthly functions of the PA0 pin PA0MD1 PA0MD0 Description 0 0 General purpose input output mode initial value 0 1 PWMC output 1 0 High speed clock OUTCLK output 1 1 Timer 9 TM9OUT out PA1MD1 PA1MD0 bit 1 The PA1MD1 and PA1MD0 bits are used to select the primary secondary tertiary and fourthly functions of the PA1 pin PA1MD1 PA1MD0 Descriptio...

Page 278: ...level of each pin of Port A can be read from the Port A data register PAD 15 3 2 Primary Function except for Input Output Port Port A is assigned to the SA A D converter input pins AIN0 AIN1 Analog comparator input CMP1P External interrupts EXI0 2 Trigger inputs TETG TFTG PCTG PDTG PETG PFTG as primary function except for input output port When used as the SA A D converter input pins AIN0 AIN1 and...

Page 279: ...Chapter 16 Port B ...

Page 280: ...ee Chapter 12 UART for the I2C Bus Interface see Chapter 13 I2C Bus Interface Master and Chapter 14 I2C Bus Interface Slave for the external clock and output of clock see Chapter 6 Clock Generation Circuit 16 1 1 Features Allows selection of high impedance output P channel open drain output N channel open drain output or CMOS output for each bit in output mode Allows selection of high impedance in...

Page 281: ... 1 PBMOD0 Port B mode register 0 PBMOD1 Port B mode register 1 Figure 16 1 Configuration of Port B PBDIR PBMOD0 1 PBCON0 1 6 Trigger Inputs TETG TFTG PCTG PDTG PETG PFTG Data bus PWMC PWMD PWME PWMF0 PWMF1 PWMF2 TXD0 TXD1 SCL SDA SOUT SCK CMP1OUT OUTCLK LSCLK PB0 to PB7 VDD VDD VSS VSS 8 8 PortB Output Controller PBD VDD VSS Pull up Pull down Controller RXD0 RXD1 CLKIN Trigger Inputs SCL SDA SIN S...

Page 282: ...TnTG PmTG I O Input output port Analog comparator 0 non inverted input Timer n trigger input PWM m trigger input SSIO data output UART0 data output UART1 data output PB5 RXD0 CMP0M TnTG PmTG I O Input output port UART0 data input Analog comparator 0 inverted input pin Timer n trigger input PWM m trigger input SSIO clock input output I 2 C clock input output PWMF2 output PB6 AIN4 TnTG PmTG I O Inpu...

Page 283: ...l Byte Symbol Word R W Size Initial value 0F258H Port B data register PBD R W 8 00H 0F259H Port B direction register PBDIR R W 8 00H 0F25AH Port B control register 0 PBCON0 PBCON R W 8 16 00H 0F25BH Port B control register 1 PBCON1 R W 8 00H 0F25CH Port B mode register 0 PBMOD0 PBMOD R W 8 16 00H 0F25DH Port B mode register 1 PBMOD1 R W 8 00H ...

Page 284: ...de PB0D Description 0 Output or input level of the PB0 pin L 1 Output or input level of the PB0 pin H PB1D Description 0 Output or input level of the PB1 pin L 1 Output or input level of the PB1 pin H PB2D Description 0 Output or input level of the PB2 pin L 1 Output or input level of the PB2 pin H PB3D Description 0 Output or input level of the PB3 pin L 1 Output or input level of the PB3 pin H P...

Page 285: ...DIR bits 7 to 0 The PB7DIR to PB0DIR pins are used to set the input output direction of the Port B pin PB0DIR Description 0 PB0 pin Output initial value 1 PB0 pin Input PB1DIR Description 0 PB1 pin Output initial value 1 PB1 pin Input PB2DIR Description 0 PB2 pin Output initial value 1 PB2 pin Input PB3DIR Description 0 PB3 pin Output initial value 1 PB3 pin Input PB4DIR Description 0 PB4 pin Outp...

Page 286: ...nput with a pull down resistor or input with a pull up resistor in input mode High impedance output means the status that both of H level output and L level output turn off Setting of PB0 pin When output mode is selected PB0DIR bit 0 When input mode is selected PB0DIR bit 1 PB0C1 PB0C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input wi...

Page 287: ...selected PB5DIR bit 0 When input mode is selected PB5DIR bit 1 PB5C1 PB5C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down resistor 1 0 N channel open drain output Input with a pull up resistor 1 1 CMOS output High impedance input Setting of PB6 pin When output mode is selected PB6DIR bit 0 When input mode is selected ...

Page 288: ...t B Description of Bits PB0MD1 PB0MD0 bit 0 The PB0MD1 and PB0MD0 bits are used to select the primary secondary tertiary and fourthly function of the PB0 pin PB0MD1 PB0MD0 Description 0 0 General purpose input output mode initial value 0 1 PWMC output 1 0 High speed clock OUTCLK output 1 1 Comparator 1 CMP1OUT output PB1MD1 PB1MD0 bit 1 The PB1MD1 and PB1MD0 bits are used to select the primary sec...

Page 289: ... input output 1 0 I 2 C clock input output 1 1 PWMF2 output PB6MD0 PB6MD0 bit 6 The PB6MD1 and PB6MD0 bits are used to select the primary secondary tertiary and fourthly functions of the PB6 pin PB6MD1 PB6MD0 Description 0 0 General purpose input output mode initial value 0 1 External clock CLKIN input 1 0 I 2 C data input output 1 1 PWMF1 output PB7MD1 PB7MD0 bit 7 The PB7MD1 and PB7MD0 bits are ...

Page 290: ... data register PBD 16 3 2 Primary Function except for Input Output Port Port B is assigned to the SA A D converter input pins AIN2 5 Analog comparator input CMP0M CMP0P External interrupts EXI4 7 Trigger inputs TETG TFTG PCTG PDTG PETG PFTG UART input pins RXD0 RXD1 as primary function except for input output port When used as the SA A D converter input pins AIN2 5 and Analog comparator input CMP0...

Page 291: ...Chapter 17 Port C ...

Page 292: ... Bus Interface Master and Chapter 14 I2 C Bus Interface Slave for the Timers see Chapter 8 Timers 17 1 1 Features Allows selection of high impedance output P channel open drain output N channel open drain output or CMOS output for each bit in output mode Allows selection of high impedance input input with a pull down resistor or input with a pull up resistor for each bit in input mode The analog i...

Page 293: ... direction register PCCON0 Port C control register 0 PCCON1 Port C control register 1 PCMOD0 Port C mode register 0 PCMOD1 Port C mode register 1 Figure 17 1 Configuration of Port C PCDIR PCMOD0 1 PCCON0 1 2 SCL SDA AIN6 AIN7 PWMF0 PWMF1 PWMF2 SCL SDA TM9OUT TMFOUT Data bus PC0 to PC7 VDD VDD VSS VSS 8 7 Port C Output Controller PCD VDD VSS Pull up Pull down Controller 2 8 ...

Page 294: ...utput port PWMF1 output PC2 I O Input output port PWMF2 output PC3 I O Input output port Timer F output PC4 I O Input output port I 2 C clock input output PC5 I O Input output port I 2 C data input output PC6 AIN6 I O Input output port SA ADC 6 input PC7 AIN7 I O Input output port SA ADC 7 input Note PC6 and PC7 are assigned to the input of SA ADC When used as an analog input of SA ADC set an appl...

Page 295: ...l Byte Symbol Word R W Size Initial value 0F260H Port C data register PCD R W 8 00H 0F261H Port C direction register PCDIR R W 8 00H 0F262H Port C control register 0 PCCON0 PCCON R W 8 16 00H 0F263H Port C control register 1 PCCON1 R W 8 00H 0F264H Port C mode register 0 PCMOD0 PCMOD R W 8 16 00H 0F265H Port C mode register 1 PCMOD1 R W 8 00H ...

Page 296: ... The PC7D to PC0D bits are used to set the output value of the Port C pin in output mode and to read the pin level of the Port C pin in input mode When used as ML610Q111 setting the value of PC7D to PC4D do not affect an applicable ports PC0D Description 0 Output or input level of the PC0 pin L 1 Output or input level of the PC0 pin H PC1D Description 0 Output or input level of the PC1 pin L 1 Out...

Page 297: ...ial value 1 PC0 pin Input PC1DIR Description 0 PC1 pin Output initial value 1 PC1 pin Input PC2DIR Description 0 PC2 pin Output initial value 1 PC2 pin Input PC3DIR Description 0 PC3 pin Output initial value 1 PC3 pin Input PC4DIR Description 0 PC4 pin Output initial value 1 PC4 pin Input PC5DIR Description 0 PC5 pin Output initial value 1 PC5 pin Input PC6DIR Description 0 PC6 pin Output initial ...

Page 298: ... resistor in input mode When used as ML610Q111 setting the value of PC7C1 to PC4C1 PC7C0 to PC4C0 do not affect an applicable ports High impedance output means the status that both of H level output and L level output turn off Setting of PC0 pin When output mode is selected PC0DIR bit 0 When input mode is selected PC0DIR bit 1 PC0C1 PC0C0 Description 0 0 High impedance output initial value High im...

Page 299: ...selected PC5DIR bit 0 When input mode is selected PC5DIR bit 1 PC5C1 PC5C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down resistor 1 0 N channel open drain output Input with a pull up resistor 1 1 CMOS output High impedance input Setting of PC6 pin When output mode is selected PC6DIR bit 0 When input mode is selected ...

Page 300: ...g the value of PC7MD1 to PC4MD1 PC7MD0 to PC4MD0 do not affect an applicable ports Description of Bits PC0MD1 PC0MD0 bit 0 The PC0MD1 and PC0MD0 bits are used to select the primary secondary tertiary and fourthly function of the PC0 pin PC0MD1 PC0MD0 Description 0 0 General purpose input output mode initial value 0 1 Prohibited 1 0 PWMF0 output 1 1 Timer 9 TM9OUT out PC1MD1 PC1MD0 bit 1 The PC1MD1...

Page 301: ...al value 0 1 I 2 C data input output 1 0 Prohibited 1 1 Prohibited PC6MD0 PC6MD0 bit 6 The PC6MD1 and PC6MD0 bits are used to select the primary secondary tertiary and fourthly functions of the PC6 pin PC6MD1 PC6MD0 Description 0 0 General purpose input output mode initial value 0 1 Prohibited 1 0 Prohibited 1 1 Prohibited PC7MD1 PC7MD0 bit 7 The PC7MD1 and PC7MD0 bits are used to select the prima...

Page 302: ...by the Port C data register PCD In input mode the input level of each pin of Port C can be read from the Port C data register PCD Note When used as ML610Q111 the PC4 to PC7 ports do not exist and the PC4 to PC7 special function registers SFRs do not perform 17 3 2 Primary Function except for Input Output Port Port C is assigned to the SA A D converter input pins AIN6 AIN7 as primary function excep...

Page 303: ...Chapter 18 Port D ...

Page 304: ...put for each bit in output mode Allows selection of high impedance input input with a pull down resistor or input with a pull up resistor for each bit in input mode 18 1 2 Configuration Figure 18 1 shows the configuration of Port D PDD Port D data register PDDIR Port D direction register PDCON0 Port D control register 0 PDCON1 Port D control register 1 Figure 18 1 Configuration of Port D 6 Data bu...

Page 305: ...apter 18 Port D FEUL610Q111 18 2 18 1 3 List of Pins Pin name I O Primary function PD0 I O Input output port PD1 I O Input output port PD2 I O Input output port PD3 I O Input output port PD4 I O Input output port PD5 I O Input output port ...

Page 306: ...gisters 18 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F268H Port D data register PDD R W 8 00H 0F269H Port D direction register PDDIR R W 8 00H 0F26AH Port D control register 0 PDCON0 PDCON R W 8 16 00H 0F26BH Port D control register 1 PDCON1 R W 8 00H ...

Page 307: ...e of the Port D pin in output mode and to read the pin level of the Port D pin in input mode PD0D Description 0 Output or input level of the PD0 pin L 1 Output or input level of the PD0 pin H PD1D Description 0 Output or input level of the PD1 pin L 1 Output or input level of the PD1 pin H PD2D Description 0 Output or input level of the PD2 pin L 1 Output or input level of the PD2 pin H PD3D Descr...

Page 308: ...ut output mode of Port D Description of Bits PD5DIR PD0DIR bits 5 to 0 The PD5DIR to PD0DIR pins are used to set the input output direction of the Port D pin PD0DIR Description 0 PD0 pin Output initial value 1 PD0 pin Input PD1DIR Description 0 PD1 pin Output initial value 1 PD1 pin Input PD2DIR Description 0 PD2 pin Output initial value 1 PD2 pin Input PD3DIR Description 0 PD3 pin Output initial ...

Page 309: ...n resistor or input with a pull up resistor in input mode High impedance output means the status that both of H level output and L level output turn off Setting of PD0 pin When output mode is selected PD0DIR bit 0 When input mode is selected PD0DIR bit 1 PD0C1 PD0C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down resis...

Page 310: ...selected PD4DIR bit 0 When input mode is selected PD4DIR bit 1 PD4C1 PD4C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down resistor 1 0 N channel open drain output Input with a pull up resistor 1 1 CMOS output High impedance input Setting of PD5 pin When output mode is selected PD5DIR bit 0 When input mode is selected ...

Page 311: ...n be selected by setting the Port D control registers 0 and 1 PDCON0 and PDCON1 In input mode high impedance input mode input mode with a pull down resistor or input mode with a pull up resistor can be selected by setting the Port D control registers 0 and 1 PDCON0 and PDCON1 At a system reset high impedance output mode is selected as the initial state In output mode L or H level is output to each...

Page 312: ...Chapter 19 Port AB Interrupts ...

Page 313: ...l register 0 PABICON1 Port AB interrupt control register 1 PABICON2 Port AB interrupt control register 2 Figure 19 1 Configuration of Port AB Interrupts Control 19 2 Description of Registers 19 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F024H Port AB interrupt control register 0 PABICON0 R W 8 00H 0F025H Port AB interrupt control register 1 PABICON1 R W 8 00...

Page 314: ...W R W R W Initial value 0 0 0 0 0 0 0 0 PABICON0 and PABICON1 are special function registers SFRs to select an interrupt edge of Port A and Port B Description of Bits PB3E0 PA0E0 PB3E1 PA0E1 bits 7 to 0 The PB3E0 to PA0E0 bits and the PB3E1 to PA0E1 bits are used to select interrupt disabled mode falling edge interrupt mode rising edge interrupt mode or both edge interrupt mode The PnE0 bit and th...

Page 315: ...signal edge for a PA1 interrupt without sampling initial value 1 Detects the input signal edge for a PA1 interrupt with sampling PA2SM Description 0 Detects the input signal edge for a PA2 interrupt without sampling initial value 1 Detects the input signal edge for a PA2 interrupt with sampling PB0SM Description 0 Detects the input signal edge for a PB0 interrupt without sampling initial value 1 D...

Page 316: ...thout sampling and interrupt generation timing in rising edge interrupt mode with sampling a When falling edge interrupt without sampling is selected b When rising edge interrupt without sampling is selected c When both edges interrupt without sampling is selected d When rising edge interrupt with sampling is selected Figure 19 2 External Interrupt Generation Timing Note When used as external inte...

Page 317: ...Chapter 20 Successive Approximation Type A D Converter ...

Page 318: ...s or 8 channels ML610Q111 6 channel ML610Q112 8 channel 20 1 2 Configuration Figure 20 1 shows the configuration of SA ADC n 0 to 7 SADRnL SA ADC result register nL SADRnH SA ADC result register nH SADCON0 SA ADC control register 0 SADCON1 SA ADC control register 1 SADMOD0 SA ADC mode register 0 PC6 AIN6 PC7 AIN7 are only used by ML610Q112 Figure 20 1 Configuration of SA ADC SADCON0 SADCON1 SADMOD...

Page 319: ...erter input pin 3 Used for the primary function of the PB1 pin PB6 AIN4 I Successive approximation type A D converter input pin 4 Used for the primary function of the PB6 pin PB7 AIN5 I Successive approximation type A D converter input pin 5 Used for the primary function of the PB7 pin PC6 AIN6 I Successive approximation type A D converter input pin 6 Used for the primary function of the PC6 pin P...

Page 320: ...register 2H SADR2H R 8 00H 0F2D6H SA ADC result register 3L SADR3L SADR3 R 8 16 00H 0F2D7H SA ADC result register 3H SADR3H R 8 00H 0F2D8H SA ADC result register 4L SADR4L SADR4 R 8 16 00H 0F2D9H SA ADC result register 4H SADR4H R 8 00H 0F2DAH SA ADC result register 5L SADR5L SADR5 R 8 16 00H 0F2DBH SA ADC result register 5H SADR5H R 8 00H 0F2DCH SA ADC result register 6L SADR6L SADR6 R 8 16 00H 0...

Page 321: ... Bits SAR03 SAR02 bits 7 to 6 The SAR03 SAR02 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 3 SA ADC Result Register 0H SADR0H Address 0F2D1H Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR0H SAR0B SAR0A SAR09 SAR08 SAR07 SAR06 SAR05 SAR04 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR0H is a special function register SFR used...

Page 322: ... Bits SAR13 SAR12 bits 7 to 6 The SAR13 SAR12 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 5 SA ADC Result Register 1H SADR1H Address 0F2D3H Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR1H SAR1B SAR1A SAR19 SAR18 SAR17 SAR16 SAR15 SAR14 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR1H is a special function register SFR used...

Page 323: ... Bits SAR23 SAR22 bits 7 to 6 The SAR23 SAR22 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 7 SA ADC Result Register 2H SADR2H Address 0F2D5H Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR2H SAR2B SAR2A SAR29 SAR28 SAR27 SAR26 SAR25 SAR24 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR2H is a special function register SFR used...

Page 324: ... Bits SAR33 SAR32 bits 7 to 6 The SAR33 SAR32 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 9 SA ADC Result Register 3H SADR3H Address 0F2D7H Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR3H SAR3B SAR3A SAR39 SAR38 SAR37 SAR36 SAR35 SAR34 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR3H is a special function register SFR used...

Page 325: ... Bits SAR43 SAR42 bits 7 to 6 The SAR43 SAR42 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 11 SA ADC Result Register 4H SADR4H Address 0F2D9H Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR4H SAR4B SAR4A SAR49 SAR48 SAR47 SAR46 SAR45 SAR44 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR4H is a special function register SFR use...

Page 326: ... Bits SAR53 SAR52 bits 7 to 6 The SAR53 SAR52 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 13 SA ADC Result Register 5H SADR5H Address 0F2DBH Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR5H SAR5B SAR5A SAR59 SAR58 SAR57 SAR56 SAR55 SAR54 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR5H is a special function register SFR use...

Page 327: ... Bits SAR63 SAR62 bits 7 to 6 The SAR63 SAR62 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 15 SA ADC Result Register 6H SADR6H Address 0F2DDH Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR6H SAR6B SAR6A SAR69 SAR68 SAR67 SAR66 SAR65 SAR64 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR6H is a special function register SFR use...

Page 328: ... Bits SAR73 SAR72 bits 7 to 6 The SAR73 SAR72 bits are used to store the values of bit 1 to bit 0 of A D conversion results 10 bits 20 2 17 SA ADC Result Register 7H SADR7H Address 0F2DFH Access R Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SADR7H SAR7B SAR7A SAR79 SAR78 SAR77 SAR76 SAR75 SAR74 R W R R R R R R R R Initial value 0 0 0 0 0 0 0 0 SADR7H is a special function register SFR use...

Page 329: ...cial function register SFR used to control the operation of the SA ADC Description of Bits SALP bit 0 This bit is used to select whether A D conversion is performed once only for each channel or continuously When this bit is set to 0 A D conversion is performed once only for each channel and when it is set to 1 A D conversion is performed continuously according to the setting of SA ADC Mode Regist...

Page 330: ...D conversion When SALP of SADCON0 is 0 and then A D conversion on the channel with the largest channel number among the selected ones is terminated the SARUN bit is automatically set to 0 SARUN Description 0 Stops conversion Initial value 1 Starts conversion Note Use the SA ADC with high speed clock oscillation HSCLK enabled in the frequency control register FCON0 Disabling high speed clock during...

Page 331: ...t to 1 A D conversion is performed on channel 0 first and then channel 1 Description of Bits SACH0 bit 0 SACH0 Description 0 Stops conversion on channel 0 Initial value 1 Performs conversion on channel 0 SACH1 bit 1 SACH1 Description 0 Stops conversion on channel 1 Initial value 1 Performs conversion on channel 1 SACH2 bit 2 SACH2 Description 0 Stops conversion on channel 2 Initial value 1 Perform...

Page 332: ...ption 0 Stops conversion on channel 6 Initial value 1 Performs conversion on channel 6 Don t set it for ML610Q111 SACH7 bit 7 SACH7 Description 0 Stops conversion on channel 7 Initial value 1 Performs conversion on channel 7 Don t set it for ML610Q111 Note Do not start A D conversion when all the SACHn from SACH0 to SACH7 set to 0 ...

Page 333: ... 0 1 1 AIN1 AIN0 0 0 1 0 0 AIN2 0 0 1 0 1 AIN2 AIN0 0 0 1 1 0 AIN2 AIN1 0 0 1 1 1 AIN2 AIN1 AIN0 1 0 0 0 0 AIN7 1 0 0 0 1 AIN7 AIN0 1 0 0 1 0 AIN7 AIN1 1 0 0 1 1 AIN7 AIN1 AIN0 1 0 1 0 0 AIN7 AIN2 1 0 1 0 1 AIN7 AIN2 AIN0 1 0 1 1 0 AIN7 AIN2 AIN1 1 0 1 1 1 AIN7 AIN2 AIN1 AIN0 The values of the result register for the sections with a slash mark remain unchanged Note Do not start A D conversion in t...

Page 334: ...nversion of the last channel Even if a channel is switched during A D conversion the channel that was selected at the start of A D conversion is used until an A D conversion termination interrupt occurs Figure 20 3 shows the SA ADC operation timing when channel 0 and channel 1 are selected Figure 20 3 SA ADC Operation Timing Note When used as an analog input of SA ADC set an applicable port as a h...

Page 335: ...Chapter 21 Voltage Level Supervisor ...

Page 336: ...21 1 shows the configuration of the VLS 0 Figure 21 2 shows the configuration of the VLS 1 VLSCON0 Voltage level supervisor control register 0 VLSCON1 Voltage level supervisor control register 1 VLSMOD Voltage level supervisor mode register Figure 21 1 Configuration of VLS0 VLSCON0 Voltage level supervisor control register 0 VLSCON1 Voltage level supervisor control register 1 VLSMOD Voltage level ...

Page 337: ...egisters 21 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F0D8H Voltage level supervisor control register 0 VLSCON0 VLSCON R W 8 16 00H 0F0D9H Voltage level supervisor control register 1 VLSCON1 R W 8 Undefined 0F0DAH Voltage level supervisor mode register VLSMOD R W 8 00H ...

Page 338: ...VLS1LV0 bit 1 0 The VLS1LV1 VLS1LV0 bits are used to select a threshold voltage of the VLS1 VLS1LV1 VLS1LV0 Description 0 0 3 3V initial value 0 1 3 6V 1 0 3 9V 1 1 4 2V DVLSSP bit 5 The DVLSSP bit is used to control the VLS operation during the STOP mode If the VLS is operating with DVLSSP set to 1 it automatically stops when the mode transits to the STOP mode If the VLS is operating with DVLSSP ...

Page 339: ... voltage level detection flag 0 It becomes 0 if the power supply voltage VDD is higher than the threshold voltage and 1 if the power supply voltage is lower than the threshold voltage When ENVLS0 is 0 VLS0ST is fixed to 0 VLS0ST Description 0 Higher than the threshold voltage 1 Lower than the threshold voltage ENVLS1 bit 4 ENVLS1 bit is used to control activation ON or deactivation OFF of the VLS1...

Page 340: ...d to control enable disable of the voltage level detector reset function of VLS0 If VLS0SEL0 is set to 1 a VLS reset function will be enabled and if VLS0SEL0 is set to 0 it will be disabled VLS0SEL0 Description 0 VLS reset function of VLS0 Disabled initial value 1 VLS reset function of VLS0 Enabled VLS1SEL1 bit 5 The VLS1SEL1 bits is used to control enable disable of the interrupt request function...

Page 341: ...reset function enabled Set ENVLSn to 1 to turned on the voltage level supervisor Wait the settling time min 1 ms of the voltage level supervisor When VDD drops the voltage level detection flag VLSnST becomes 1 Read VLSnST from CPU Figure 21 3 Example of Operation Timing Diagram with voltage level detection flag VLSnST Set ENVLS0 to 1 to turned on the voltage level supervisor Wait the settling time...

Page 342: ...Chapter 22 Analog Comparator ...

Page 343: ...6kHz at OSCLK 8 192MHz The last status of comparator output CMPnD remains after the comparator is deactivated The comparator 0 includes 20mV hysteresis at typ 22 1 2 Configuration Figure 22 1 shows the configuration of the Comparator CMP0CON0 Comparator 0 control register 0 CMP1CON0 Comparator 1 control register 0 CMP0CON1 Comparator 0 control register 1 CMP1CON1 Comparator 1 control register 1 CM...

Page 344: ...ed input pin PB0 CMP1OUT O Analog comparator 1 output pin 22 2 Description of Registers 22 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F950H Comparator 0 control register 0 CMP0CON0 R W 8 00H 0F951H Comparator 0 control register 1 CMP0CON1 R W 8 00H 0F952H Comparator 0 control register 2 CMP0CON2 R W 8 08H 0F954H Comparator 1 control register 0 CMP1CON0 R W 8...

Page 345: ...ontrol ON OFF of the comparator 0 When CMP0EN is set to 1 the comparator 0 is turned on When it is set to 0 the comparator 0 is turned off CMP0EN Description 0 Comparator 0 OFF initial value 1 Comparator 0 ON CMP0D bit 1 CMP0D indicates the status of the comparator 0 output CMP0OUT in Figure 22 1 It is set to 1 when the PB4 pin voltage is higher than the PB5 pin voltage PB4 PB5 It is set to 0 when...

Page 346: ...cription 0 0 Detects without sampling initial value 0 1 Detects with sampling Sampling clock T16KHZ 16 384kHz Typ 1 0 Detects with sampling Sampling clock OSCLK 64 128kHz at OSCLK 8 192MHz 1 1 Detects with sampling Sampling clock OSCLK 32 256kHz at OSCLK 8 192MHz CMP0RFS bit 4 The CMP0RFS bit is used to select the reference voltage Vref of the comparator 0 CMP0RFS Description 0 Vref Internal refer...

Page 347: ...RF0 bit 3 to 0 The CMP0RF0 CMP0RF1 CMP0RF2 and CMP0RF3 bits are used to select the reference voltage of the comparator 0 This setting is valid when the reference voltage Vref of the comparator 0 is set to the internal reference input CMP0RFS 0 A setting of 0h 0 05V is possible without a guaranteed accuracy CMP0RF3 CMP0RF2 CMP0RF1 CMP0RF0 Comparator 0 Reference voltage 0 0 0 0 0 05V no guaranteed a...

Page 348: ... the Comparator 1 is turned on When it is set to 0 the Comparator 1 is turned off CMP1EN Description 0 Comparator 1 OFF initial value 1 Comparator 1 ON CMP1D bit 1 CMP1D indicates the status of the Comparator 1 output CMP1OUT in Figure 22 1 It is set to 1 when the PA1 pin voltage is higher than the internal reference voltage PA1 Internal reference voltage It is set to 0 when the PA1 pin voltage is...

Page 349: ...ts are used to select with without sampling for the Comparator 1 comparison CMP1SM1 CMP1SM0 Description 0 0 Detects without sampling initial value 0 1 Detects with sampling Sampling clock T16KHZ 16 384kHz Typ 1 0 Detects with sampling Sampling clock OSCLK 64 128kHz at OSCLK 8 192MHz 1 1 Detects with sampling Sampling clock OSCLK 32 256kHz at OSCLK 8 192MHz Note In STOP mode since the sampling cloc...

Page 350: ... bit 3 to 0 The CMP1RF0 CMP1RF1 CMP1RF2 and CMP1RF3 bits are used to select the reference voltage of the Comparator 1 This setting is valid when the reference voltage Vref of the Comparator 1 is set to the internal reference input CMP1RFS 0 A setting of 0h 0 05V is possible without a guaranteed accuracy CMP1RF3 CMP1RF2 CMP1RF1 CMP1RF0 Comparator 1 Reference voltage 0 0 0 0 0 05V no guaranteed accu...

Page 351: ...mparator requires a settling time Read CMPnD bit 100us or more after CMPnEN bit is set to 1 Figure 22 2 shows an example of the operation timing diagram Figure 22 2 Example of Operation Timing Diagram n 0 1 The operations in Figure 22 2 are described below Select the interrupt mode by CMPnCON1 Set CMPnEN to 1 to turn on the comparator Wait the settling time min 100 us of the comparator Read the co...

Page 352: ...ng edge interrupt mode and in both edge interrupt mode without sampling and in rising edge interrupt mode with sampling a When Falling Edge Interrupt Mode without Sampling is Selected b When Rising Edge Interrupt Mode without Sampling is Selected c When Both Edge Interrupt Mode without Sampling is Selected d When Rising Edge Interrupt Mode with Sampling is Selected Figure 22 3 Comparator Interrupt...

Page 353: ...Chapter 23 Data Flash Memory ...

Page 354: ...table by using a special function register SFR programmatically 23 1 1 Features Rewrite counts 1 6000 times VDD 2 7 to 5 5 V 20 to 85 C Sector Erase Erase of 512 words 1 Kbytes Block erase Erase of 2 Kwords 4 Kbytes Writing 1 word 2 bytes write 1 One rewrite cycle includes both one time erase and one time write it counts as one even if the erase is aborted Rewrite counts is counted as one even if ...

Page 355: ...ster H FLASHAH R W 8 00H 0F0E2H Flash data register L FLASHDL FLASHD R W 8 16 00H 0F0E3H Flash data register H FLASHDH R W 8 00H 0F0E4H Flash control register FLASHCON W 8 00H 0F0E5H Flash acceptor FLASHACP W 8 00H 0F0E6H Flash segment register FLASHSEG R W 8 00H 0F0E7H Flash self register FLASHSLF R W 8 00H 0F0E8H Flash protection register FLASHPRT R W 8 00H 0F0EEH Flash erase abort source select...

Page 356: ...te Note that the bit 0 is fixed to 0 and cannot be written FA15 FA8 bits 7 0 The FA15 to FA8 bits are used to set the upper address for sector erase block erase or 1 word write The upper address is specified by the flash segment registers FSEG0 FSEG1 and FA15 to FA8 Table 23 1 shows the address setting values for sector erase and table 23 2 shows the address values for block erase Table 23 1 Addre...

Page 357: ...tion registers SFRs that sets the flash memory rewrite data Description of Bits FD7 FD0 bits 7 0 The FD7 to FD0 bits are used to set the lower write data for 1 word write FD15 FD8 bits 7 0 The FD15 to FD8 bits are used to set the upper write data for 1 word write Writing to FD15 FD8 starts the 1 word 2 bytes write Note Erase a sector or erase a block of target writing addresses in advance The cont...

Page 358: ...fied by the FSEG1 to FSEG0 bit of FLASHSEG register and the FA15 to FA8 bit of FLASHAH register This bit is automatically set to 0 after completing the erase FSERS bit 1 FSERS is a bit to specify the start of the sector erase Setting the FSERS bit to 1 erases the sector specified by the FSEG1 to FSEG0 bit of FLASHSEG register and the FA15 to FA8 bit of FLASHAH register This bit is automatically se...

Page 359: ...ts fac7 to fac0 bit 7 to 0 The fac7 to fac0 bits are used to restrict the sector erase block erase or 1 word write operation in order to prevent an unintended operation Writing 0FAH and 0F5H to FLASHACP in this order enables a one time sector erase block erase or 1 word write For subsequent sector erases block erases or 1 word writes you must write 0FAH and 0F5H to FLASHACP each time Even if anoth...

Page 360: ...SEG1 FSEG0 Description 0 0 Disabled initial value 0 1 Disabled 1 0 Segment 2 is selected 1 1 Disabled 23 2 7 Flash Self Register FLASHSLF Address 0F0E7H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 FLASHSLF FSELF R W R W Initial value 0 0 0 0 0 0 0 0 FLASHSLF is a special function register SFR that control the data flash memory rewrite function Description of Bits FSELF bit 0 Th...

Page 361: ...1 word write in the segment 2 0000H to 03FFH Disabled FPRT1 bit 1 The FPRT1 is a bit to control the sector erase block erase and 1 word write in the segment 2 0400H to 07FFH Writing 1 to FPRT1 sets FPRT1 to 1 and disables the subsequent sector erases block erases and 1 word writes in the segment 2 0400H to 07FFH Even if 0 is written to FPRT1 after 1 is written to FPRT1 it is not set to 0 FPRT1 is ...

Page 362: ...erases and 1 word writes in the segment 2 0C00H to 0FFFH Even if 0 is written to FPRT3 after 1 is written to FPRT3 it is not set to 0 FPRT3 is set to 0 at system reset FPRT3 Description 0 The sector erase block erase and 1 word write in the segment 2 0C00H to 0FFFH Enabled initial value 1 The sector erase block erase and 1 word write in the segment 2 0C00H to 0FFFH Disabled Note Writing 1 to one o...

Page 363: ...s bit is set to 1 PA1INT is selected as the erase abort source FEPA2S bit 2 When this bit is set to 1 PA2INT is selected as the erase abort source FEPB0S bit 4 When this bit is set to 1 PB0INT is selected as the erase abort source FEPB1S bit 5 When this bit is set to 1 PB1INT is selected as the erase abort source FEPB2S bit 6 When this bit is set to 1 PB2INT is selected as the erase abort source F...

Page 364: ...special function register SFR to indicate the flash erase status Description of Bits ESTAT bit 7 The ESTAT bit is used to indicate the erase status If erase is completed successfully it is set to 0 If erase is aborted it is set to 1 It is returned to 0 by writing 0 ESTAT Description 0 Not erasing or erase has been completed successfully 1 Erase has been aborted by the source selected to FLASHEAS N...

Page 365: ...the flash rewrite acceptor function which restricts the rewrite operation to prevent an improper rewriting of the flash memory Writing 0FAH and 0F5H to flash acceptor FLASHACP in this order enables a one time sector erase block erase or 1 word write For the specification of the flash memory see the section for flash memory specification in Appendix C Electrical Characteristics Note Use it with hig...

Page 366: ...m is restarted from the instruction following the one that set the FLASHCON FSERS bit to 1 Figure 23 1 shows the sector erase flow Figure 23 1 Sector Erase Flow Program started Write 0F5H to FLASHACP register Erase completed Sector erase completed Write 01H to FLASHSLF register Enable the flash memory rewrite function CPU waits until erase completes Y N Enable the successive write block erase oper...

Page 367: ... Set the segment ST R9 EA Set block address MOV R2 02H Setting data for sector erase ST R2 FLASHCON Start sector erase NOP Always set NOP Always set RB FSELF Disables the flash rewrite function Figure 23 2 Sample Program of Sector Erase Note Be sure to set the NOP instruction twice or more following the sector erase start instruction Use it with high speed clock oscillation HSCLK enabled in the fr...

Page 368: ...am is restarted from the instruction following the one that set the FLASHCON FERS bit to 1 Figure 23 3 shows the block erase flow Figure 23 3 Block Erase Flow Program started Write 0F5H to FLASHACP register Erase completed Block erase completed Write 01H to FLASHSLF register Enable the flash memory rewrite function CPU waits until erase completes Y N Enable the successive write block erase operati...

Page 369: ...V R2 01H Setting data for block erase ST R2 FLASHCON Start block erase NOP Always set NOP Always set RB FSELF Disables the flash rewrite function Figure 23 4 Sample Program of Block Erase Note Be sure to set the NOP instruction twice or more following the block erase start instruction Use it with high speed clock oscillation HSCLK enabled in the frequency control register FCON1 and with HSCLK sele...

Page 370: ...s about 5μs 40μs x 10 450μs at maximum for writing 10 words 20 bytes Figure 23 5 shows the 1 word write flow Figure 23 5 1 word Write Flow Figure 23 6 shows a sample program of 1 word write assuming that the FLASHSEG register is already set Write 0FAH to FLASHACP register Write 0F5H to FLASHACP register Write 02H to FLASHSEG register Write xxH to FLASHAH register Write xxH to FLASHAL register Writ...

Page 371: ...ting data for the segment ST R6 FLASHSEG ST XR8 EA Set address and data start 1 word write NOP Always set NOP Always set L ER14 R6 ER8 Load data CMP ER14 ER10 Check data BNE ERROR Go to error routine on error ADD ER8 ER2 Address increment CMP ER8 ER12 BLE MARK Compare addresses RB FSELF Disables the flash rewrite function Figure 23 6 Sample Program of 1 word Write Note Be sure to set the NOP instr...

Page 372: ... 23 Data Flash Memory FEUL610Q111 23 19 23 3 4 Notes in Use When the power is down or the operation is terminated forcibly during sector erase block erase or 1 word write retry the sector erase or block erase and rewrite the sector block area ...

Page 373: ...Chapter 24 On chip Debug ...

Page 374: ...he board so that the 4 pins VDD VSS RESET_N TEST required for connection to the on chip debug emulator can be connected 2 7V to 5 5V has to be supplied to VDD while debugging and writing flash When the user application circuit have a system reset circuit enable to switch the connection of RESET_N pin as shown in the Figure 24 1 If it is difficult to have such switching function make the capacitanc...

Page 375: ...Appendixes ...

Page 376: ...3 IRQ3 R W 8 00H 0F01CH Interrupt request register 4 IRQ4 R W 8 00H 0F01DH Interrupt request register 5 IRQ5 R W 8 00H 0F01EH Interrupt request register 6 IRQ6 R W 8 00H 0F01FH Interrupt request register 7 IRQ7 R W 8 00H 0F024H Port AB interrupt control register 0 PABICON0 R W 8 00H 0F025H Port AB interrupt control register 1 PABICON1 R W 8 00H 0F026H Port AB interrupt control register 2 PABICON2 ...

Page 377: ...er 0 SIO0MOD0 SIO0MOD R W 8 16 00H 0F285H Serial port 0 mode register 1 SIO0MOD1 R W 8 00H 0F290H UART0 transmit receive buffer UA0BUF R W 8 00H 0F291H UART0 control register UA0CON R W 8 00H 0F292H UART0 mode register 0 UA0MOD0 UA0MOD R W 8 16 00H 0F293H UART0 mode register 1 UA0MOD1 R W 8 00H 0F294H UART0 baud rate register L UA0BRTL UA0BRT R W 8 16 0FFH 0F295H UART0 baud rate register H UA0BRTH...

Page 378: ...register TMFD TMFDC R W 8 16 0FFH 0F369H Timer F counter register TMFC R W 8 00H 0F36AH Timer F control register 0 TMFCON0 TMFCON R W 8 16 00H 0F36BH Timer F control register 1 TMFCON1 R W 8 00H 0F36CH Timer F control register 2 TMFCON2 TMFCON23 R W 8 16 00H 0F36DH Timer F control register 3 TMFCON3 R W 8 00H 0F8E0H Timer 8 data register TM8D TM8DC R W 8 16 0FFH 0F8E1H Timer 8 counter register TM8...

Page 379: ... control register 1 PWECON1 R W 8 00H 0F938H PWME control register 2 PWECON2 PWECON23 R W 8 16 00H 0F939H PWME control register 3 PWECON3 R W 8 00H 0F950H Comparator 0 control register 0 CMP0CON0 R W 8 00H 0F951H Comparator 0 control register 1 CMP0CON1 R W 8 00H 0F952H Comparator 0 control register 2 CMP0CON2 R W 8 08H 0F954H Comparator 1 control register 0 CMP1CON0 R W 8 00H 0F955H Comparator 1 ...

Page 380: ...Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code and desired mounting conditions reflow method temperature and times ...

Page 381: ...face Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code and desired mounting conditions reflow method temperature and times ...

Page 382: ...oltage VDD 2 7 to 5 5 V Flash Memory Specification VSS 0V Parameter Symbol Condition Range Unit Operating temperature ambience TOPF At read 40 to 105 C At write erase 20 to 85 C Rewrite counts 1 CEPD Data area 4KB 6000 cycles CEPP Program area 80 Erase unit Chip erase All of the program and data area Block erase Program area 8 KB Data area 4 KB Sector erase effective only data area 1 KB Erase time...

Page 383: ...ly CR oscillation operates VDD 5 0V 240 µA Supply current 3 IDD3 CPU CR 32 768kHz operating state 2 Only CR oscillation operates VDD 5 0V 250 µA Supply current 4 IDD4 CPU PLL 8 192MHz operating state 3 CR and PLL oscillation operate VDD 5 0V 4 6 mA 1 LTBC and WDT are operating and significant bits of BLKCON0 to BLKCON7 registers are all 1 2 When the CPU operating rate is 100 Minimum instruction ex...

Page 384: ...hold voltage VDD rise VVLS0R Ta 25 C Typ 3 0 2 92 Typ 3 0 Typ 5 0 Typ 5 0 VLS1 threshold voltage VDD fall VVLS1 Ta 25 C VLS1 0 Typ 3 0 3 3 Typ 3 0 VLS1 1 3 6 VLS1 2 3 9 VLS1 3 4 2 VLS1 0 Typ 5 0 3 3 Typ 5 0 VLS1 1 3 6 VLS1 2 3 9 VLS1 3 4 2 Comparator 0 In phase input voltage range VCMR 0 1 VDD 1 5 V Comparator 0 hysteresis VHYSP Ta 25 C VDD 5 0V 10 20 30 mV VDD 5 0V 5 20 35 Comparator 0 Input offs...

Page 385: ...ate 1 µA 3 IOOL VOL VSS in high impedance state 1 Input current 1 RESET_N IIH1 VIH1 VDD 1 µA 4 IIL1 VIL1 VSS VDD 5 0V 650 500 350 Input current 2 TEST IIH2 VIH2 VDD 5 0V 20 115 200 IIL2 VIL2 VSS 1 Input current 3 PA0 2 PB0 7 PC0 7 PD0 5 IIH3 VIH3 VDD 5 0V when pulled down 20 115 200 IIL3 VIL3 VSS VDD 5 0V when pulled up 200 100 20 IIH3Z VIH3 VDD in high impedance stat 1 IIL3Z VIH3 VSS in high impe...

Page 386: ...put logic circuit to determine the specified measuring conditions 2 Measured at the specified output pins 3 Measured at the specified input pins 2 3 Measuring circuit 4 Measuring circuit 2 VDD VSS VIH VIL 2 A VDD VSS A Input pins VDD VSS A CV 1μF Output pins Output pins Input pins Input pins Input pins Output pins Output pins Measuring circuit 3 CV ...

Page 387: ...p 3 16 384 Typ 3 MHz Typ 4 Typ 4 1 Average value of 2048 clocks The CPU clock is set to the maximum fPLL 2 2 Guarantee value at the time of the shipment AC Characteristics Power on Reset sequence VDD 2 7 to 5 5V VSS 0V Ta 40 to 105 C unless otherwise specified Parameter Symbol Condition Rating Unit Min Typ Max Reset pulse width PRST 100 µs Reset noise elimination pulse width PNRST 0 4 Power on res...

Page 388: ...0 to 105 C unless otherwise specified Parameter Symbol Condition Rating Unit Min Typ Max External interrupt disable period tNUL Interrupt Enabled MIE 1 CPU NOP operation 2 5 X sysclk 3 5 X sysclk φ tNUL EXI0 to EXI2 EXI4 to EXI7 Rising edge interrupt Falling edge interrupt Both edge interrupt tNUL tNUL EXI0 to EXI2 EXI4 to EXI7 EXI0 to EXI2 EXI4 to EXI7 ...

Page 389: ...ion is active 500 ns SCK output cycle master mode tSCYC SCK 1 ns SCK input pulse width slave mode tSW When high speed oscillation is not active 4 µs When high speed oscillation is active 200 ns SCK output pulse width master mode tSW tSCYC 0 4 tSCYC 0 5 tSCYC 0 6 s SOUT output delay time slave mode tSD 180 ns SOUT output delay time master mode tSD 80 ns SIN input setup time slave mode tSS 50 ns SIN...

Page 390: ...tSU DAT 0 25 µs SDA setup time stop condition tSU STO 4 0 µs Bus free time tBUF 4 7 µs AC Characteristics I2C Bus Interface Fast Mode 400kHz VDD 2 7 to 5 5V VSS 0V Ta 40 to 105 C unless otherwise specified Parameter Symbol Condition Rating Unit Min Typ Max SCL clock frequency fSCL 0 400 kHz SCL hold time start restart condition tHD STA 0 6 µs SCL L level time tLOW 1 3 µs SCL H level time tHIGH 0 6...

Page 391: ...eter Symbol Condition Rating Unit Min Typ Max Resolution n 10 bit Integral non linearity error INL RI 5kΩ HSCLK 8 192MHz 4 4 LSB Differential non linearity error DNL RI 5kΩ HSCLK 8 192MHz 3 3 Zero scale error VOFF RI 5kΩ HSCLK 8 192MHz 4 4 Full scale error FSE RI 5kΩ HSCLK 8 192MHz 4 4 Allowale signal source impedance R 5k Ω Conversion time tCONV 102 φ CH φ Period of OSCLK more than 3MHz A VDD VSS...

Page 392: ...rcuit Example CV 1μF CR 100pF CAIN 0 1μF Reset IC BD45285 Product made in ROHM Co Ltd Nch open drain output TEST WP SCL SDA Vcc Vss A0 A1 A2 I 2 C EEPROM PB4 PB5 SCL PB6 SDA 5 0V ML610Q111 ML610Q112 VTref RESET_N TEST VSS uEASE Interface RESET_N Reset IC VDD VSS CV CR CAIN AD Input PB0 PWMC PB1 AIN3 PB2 PB3 3 3VOUT ...

Page 393: ...Appendix E ...

Page 394: ...ase fill unused program memory area your program code does not use with BRK instruction code 0FFH Please fill the area with the code 0FFH when you release a code for LAPIS Semiconductor s factory programming Initializing RAM The hardware reset does not initialize RAM Please initialize RAM by the software Chapter 3 Reset Function Reset activation pulse width Minimum 100us Refer to Appendix C 2 in t...

Page 395: ... the user s manual Restrictions of the timer There are restrictions when using 16 bit timer mode For the contents and workaround for the restriction refer 8 4 Restriction of timer Chapter 9 Watchdog Timer Overflow period Clear WDT during the selected overflow period 125ms 500ms 2s 8s 23 4ms 31 25ms 62 5ms WDP Check the WDP content before writing to the WDTCON register then determine writing whethe...

Page 396: ...apter 22 Analog Comparator In STOP mode since the sampling clock stops no sampling is performed regardless of the values set in CMP0SM1 0 When the sampling OSCLK 64 OSCLK 32 is selected HSCLK must be operated When CMP0RF3 0 is set 4 h0 0 05V as comparator reference voltage the precision is not guaranteed Read CMPnD bit 100us or more after CMPnEN bit is set to 1 n 0 1 Chapter 23 Data Flash Memory R...

Page 397: ...e confirm there are some SFRs have undefined initial value at reset Refer to Appendix A in the user s manual Appendix C Electrical Characteristics External capacitors for Power circuits Cv 1uF connected to VDD pin Operating voltage 2 7V to 5 5V Operating temperature 40 C to 105 C Writing to FLASH memory erase temperature 20 C to 85 C ...

Page 398: ...Revision History ...

Page 399: ...2 1 2 2 Added note of HTU8 Program development support software 2 4 2 4 Added note of ROM Window and reference area 3 2 3 2 Corrected an initialized value of VLSR WDTR wrong 0 correct 0 1 3 2 3 2 Corrected an initialized value of POR wrong 0 correct 0 1 3 2 3 2 Added note of POR bit 4 3 4 3 Added a description of a stop code acceptor STPACP 4 4 4 4 Added a description of a STP bit of a stand by co...

Page 400: ...ontrol register 3 TMECON3 8 34 8 34 Added a description of timer F control register 3 TMFCON3 8 39 Added a restriction of timer 9 5 9 5 Added note of watch dog timer 10 5 10 14 10 23 10 32 10 5 10 14 10 23 10 32 Added note of PWMn period register PWnPL PWnPH n C D E 10 6 10 15 10 24 10 33 10 6 10 15 10 24 10 33 Added note of PWMn duty register PWnDL PWnDH n C D E 10 7 10 16 10 25 10 34 10 7 10 16 ...

Page 401: ... description of high impedance output mode 18 4 18 4 Added note to set a value of PDD by bit manipulation instruction 18 6 18 6 Added a description of high impedance output mode 20 2 20 2 Added note of using port as the analog input of SA ADC 20 13 20 13 Added note for stop of high speed clock during AD conversion 20 17 20 17 Added note for setting an analog input port Added note of output impedan...

Page 402: ... 23 4 Added note of the block erase operation 23 17 23 17 Added a description of the time for the write operation 23 18 23 18 Corrected a sample program in Figure 23 6 Added note of the 1 word writing operation 24 1 24 1 Corrected a Figure 24 1 24 1 24 1 Added a description of the case that there is not a system reset circuit on a user application circuit A 1 A 1 Corrected an initial value of volt...

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