Lapis ML610Q111, User Manual

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ML610Q111/ML610Q112 User’s Manual
Chapter 14 I
2
C bus Interface Slave
FEUL610Q111 14-14
14.4 Specifying port registers
To enable the I
2
C function, the applicable bit of each related port register needs to be set. See Chapter 16, “Port B” and
Chapter 17, “Port C” for detail about the port registers.
14.4.1 Functioning PB5(SCL) and PB6(SDA) as the I2C
Set PB6MD1 to PB5MD1 bit (bit6-5 of PBMOD1 register) to “1”, and PB6MD0 to PB5MD0 bit (bit6-5 of PBMOD0
register) to “0”, for specifying the I2C as the tertiary function (I
2
C bus data/clock output) of PB5 and PB6.
Reg. name PBMOD1 register (Address: 0F25DH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7MD1 PB6MD1 PB5MD1 PB4MD1 PB3MD1 PB2MD1 PB1MD1 PB0MD1
Data * 1 1 * * * * *
Reg. name PBMOD0 register (Address: 0F25CH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7MD0 PB6MD0 PB5MD0 PB4MD0 PB3MD0 PB2MD0 PB1MD0 PB0MD0
Data * 0 0 * * * * *
Set PB6C1-PB5C1 bit(bit6-5 of PBCON1 register) to “1”, set PB6C0-PB5C0 bit(bit6-5 of PBCON0 register) to “0”, and
set PB6DIR-PB5DIR bit(bit6-5 of PBDIR register) to “0”, for specifying the PB6 and PB5 as Nch open-drain output. The
open-drain/open-collector outputs are required on the I2C bus line to avoid collision between H level and L level.
Reg. name PBCON1 register (Address: 0F25BH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1
Data * 1 1 * * * * *
Reg. name PBCON0 register (Address: 0F25AH)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0
Data * 0 0 * * * * *
Reg. name PBDIR register (Address: 0F259H)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7DIR PB6DIR PB5DIR PB4DIR PB3DIR PB2DIR PB1DIR PB0DIR
Data * 0 0 * * * * *
Data of PB6D-PB5D bits (bit6-5 of PBD register) do not affect to the I2C function, so don’t care the data for the function.
Reg. name PBD register (Address: 0F258H)
Bit 7 6 5 4 3 2 1 0
Bit name
PB7D PB6D PB5D PB4D PB3D PB2D PB1D PB0D
Data * ** ** * * * * *
* : Bit not related to the I2C bus interface function
** : Don’t care the data