Hitachi H8/3060, Hardware Manual

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870
8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3 H’FFF92
H’FFF93 8-bit timer channel 2
8-bit timer channel 3
Bit
Initial value
Read/Write
0
R/(W)
*
7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
0
R/W
4
ICE
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
Timer overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
Bit
Initial value
Read/Write
0
R/(W)
*
7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
1
—
4
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
8TCSR3
8TCSR2
1
[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match/input capture flag A
0
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
1
[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5 to clear these flags.
Output select A1 and A0
0
Description
Bit 1
OS1
Bit 0
OS0
1
0
1
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
0
1
Description
ICE in
8TCSR3
Bit 3
OIS3
Bit 3
OIS2
Output/input capture edge select B3 and B2
0
0
1
0
1
0
1
0
1
0
1
0
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
1
Input capture enable
0
1
TCORB is a compare match register
TCORB is an input capture register