Epson S1C6S3N2, Technical Manual

Page: 97 / 270

S1C6S3N2 TECHNICAL HARDWARE
EPSON
I-85
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
The SVD circuit must be made ON with at least 100 µs for
the SVD circuit to respond. Hence, when the CPU system
clock is f
OSC3
in S1C6S3A2, the detection result at the
timing in (1) above may be invalid or incorrect. (When per-
forming SVD detection using the timing in (1), be sure that
the CPU system clock is f
OSC1
.)
When SVD sampling is done with HLMOD set to "1", the
results are written to the SVD latch in the timing as follows:
(1) As soon as the time has elapsed for one instruction cycle
immediately following HLMOD = "0"
→
"1"
(2) Immediately on completion of sampling at cycles of 2 Hz
output by the clock timer while HLMOD = "1"
Consequently, the SVD latch data is written immediately
after HLMOD is set to "0"
→
"1", and at the same time the
new detection result is written in 2 Hz cycles.
When "0" is written : SVD detection OFF
When "1" is written : SVD detection ON
When "0" is read out : Source voltage (V
DD
–V
SS
)
is higher than SVD set value
When "1" is read out : Source voltage (V
DD
–V
SS
)
is lower than SVD set value
Note that the function of this bit when written is different to
when read out.
When this bit is written to, ON/OFF of the SVD detection
operation is controlled; when this bit is read out, the result
of the SVD detection (contents of SVD latch) is obtained.
Appreciable current is consumed during operation of SVD
detection, so keep SVD detection OFF except when neces-
sary.
When BLS is set to "1", SVD detection is executed. As soon
as BLS is reset to "0" the detection result is loaded to the
SVD latch. To obtain a stable SVD detection result, the SVD
circuit must be set to ON with at least 100 µs. Hence, to
obtain the SVD detection result, follow the programming
sequence below.
BLS:
SVD detection (076H·D2)
BLD:
SVD data