Epson S1C6S3N2, Technical Manual

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I-2
EPSON
S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 1: OVERVIEW
1.2 Features
* 1 Selected by mask option
*
2 The supply voltage range of the S1C6S3N2 and S1C6S3A2 is 2.2 to 3.6 V when
an LCD panel is used.
In this manual, BLD and SVD (supply voltage detection) have the same meaning.
OSC1 oscillation circuit
OSC3 oscillation circuit
Instruction sets
Instruction execution time
(differs depending oninstruction)
(CLK: CPU operation frequency)
ROM capacity
RAM capacity
Input ports
Output ports
Input/output ports
LCD driver
Time base counter
Watchdog timer
Event counter
Analog comparator
Supply voltage detection circuit (SVD)
External interrupt
Internal interrupt
Supply voltage *2
Consumed
current
(Typ. value)
Form when shipped
CLK = 32.768 kHz
(when halted)
CLK = 32.768 kHz
(when executed)
CLK = 1 MHz
(when executed)
Crystal oscillation circuit 32.768 kHz (Typ.)
No setting
100 types
153
µ
sec, 214
µ
sec, 366
µ
sec (CLK = 32.768 kHz)
2,048 words, 12 bits per word
144 words, 4 bits per word
5 bits (pull-down resistor can be added through mask option)
8 bits (BZ, BZ, FOUT outputs are available through mask option)
8 bits (pull-down resistor is added during input data read-out)
Either 38 segments
×
4 or 3 or 2 common *1
V-3V 1/4 or 1/3 or 1/2 duty (regulated voltage circut and booster voltage circuit built-in)
Two types (timer and stopwatch)
Built-in (can be disabled through mask option)
One 8-bit inputs
Inverted input x 1, noninverted input x 1
Input port interrupt; dual system
Time base counter interrupt; dual system
80-pin QFP (plastic) or chip
CR or ceramic
oscillation circuit *1
1 MHz
(Typ.)
5
µ
sec, 7
µ
sec, 12
µ
sec
(CLK = 1 MHz)
S1C6S3N2 S1C6S3L2 S1C6S3B2 S1C6S3A2
2.4 V
3.0 V (1.8–3.6 V)
0.65
µ
A
2.0
µ
A
–
1.2 V
1.5 V (0.9–1.8 V)
0.65
µ
A
2.0
µ
A
–
1.2 V
1.5 V (0.9–3.6 V)
0.65
µ
A
2.0
µ
A
–
2.4 V
3.0 V (1.8–3.6 V)
1.5
µ
A
4.0
µ
A
150
µ
A