Epson S1C6S3N2, Technical Manual

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S1C6S3N2 TECHNICAL HARDWARE
EPSON
I-67
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
The stopwatch counter is configured of four-bit BCD count-
ers SWL and SWH.
The counter SWL, at the stage preceding the stopwatch
counter, has an approximated 100 Hz signal for the input
clock. It counts up every 1/100 sec, and generates an
approximated 10 Hz signal. The counter SWH has an ap-
proximated 10 Hz signal generated by the counter SWL for
the input clock. It count-up every 1/10 sec, and generated 1
Hz signal.
Figure 4.9.2 shows the count-up pattern of the stopwatch
counter.
SWL generates an approximated 10 Hz signal from the basic
256 Hz signal. The count-up intervals are 2/256 sec and 3/
256 sec, so that finally two patterns are generated: 25/256
sec and 26/256 sec intervals. Consequently, these patterns
do not amount to an accurate 1/100 sec.
SWH counts the approximated 10 Hz signals generated by
the 25/256 sec and 26/256 sec intervals in the ratio of 4:6,
to generate a 1 Hz signal. The count-up intervals are 25/
256 sec and 26/256 sec, which do not amount to an accu-
rate 1/10 sec.
Count-up pattern
26
256 26
256 26
256 26
256 26
256 26
256 25
256 25
256 25
256 25
256
3
256 2
256 3
256 2
256 2
256 2
256 3
256 3
256 3
256 2
256
3
256 2
256 3
256 3
256 3
256 3
256 3
256 2
256 2
256 2
256
26
256
25
256
26
256 25
256
x 6 +
x 4 = 1 (S)
0 1 2 3 4 5 6 7 8 9 0
0 1 2 3 4 5 6 7 8 9 0
0 1 2 3 4 5 6 7 8 9 0
1 Hz
signal
generation
Approximate
10 Hz
signal
generation
Approximate
10 Hz
signal
generation
SWH count value
Count time (S)
(S)
(S)
SWL count value
Count time (S)
SWL count value
Count time (S)
SWH count up pattern
SWL count up pattern 1
SWL count up pattern 2
Fig. 4.9.2
Count-up pattern of
stopwatch counter