Epson S1C6S3N2, Technical Manual

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S1C6S3N2 TECHNICAL SOFTWARE
EPSON
II-29
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
When HLMOD is set to "1" or low voltage is detected by the
BLD, the HLMOD circuit is turned ON. At the same time the
SVD circuit is switched ON and OFF.
At this time, sampling control is executed for the SVD cir-
cuit ON time. There are two types of sampling time, as
follows:
➀
The time of one instruction cycle immediately after the
HLMOD circuit is turned ON.
➁
Sampling at cycles of 2 Hz output by the clock timer
while HLMOD circuit ON time.
When the CPU system clock is f
OSC3
in S1C6S3A2, the
detection result at the timing in
➀
above may be invalid or
incorrect. When performing SVD detection using the timing
in
➀
, be sure that the CPU system clock is f
OSC1
.
Appreciable current is consumed during operation of SVD detec-
tion, so keep SVD detection OFF except when necessary.
Note
(1) For OSC1 using BLS
Specifications When the CPU clock is OSC1, the timing flag ("0.5-sec flag")
is set in the T2Hz interrupt processing routine "TI2", so that
the supply voltage is detected every second.
Every second on the second the timer routine "basic timer
'CK'" is executed, to turn BLS ON or OFF every second on
the half second.
If the detection result indicates that the voltage is low, the
separately prepared low voltage display routine "DSBLD" is
executed.
n sec n.5 sec (n+1) sec (n+1).5 sec
"CK" is executed "CK" is executed
Supply voltage
is detected
Time
Supply voltage
is detected
Fig. 5.3.1
Timing chart