S1C6S3N2 TECHNICAL SOFTWARE
EPSON
II-39
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
➁
When the CPU system clock is f
OSC3
(in case of
S1C6S3A2 only)
1. When detection is done at HLMOD
After writing "1" on HLMOD, read the BLD after 0.6
sec has passed. (HLMOD holds "1" for at least 0.6
sec)
2. When detection is done at BLS
Before writing "1" on BLS, write "1" on HLMOD first;
after at least 100 µs has lapsed after writing "1" on
BLS, write "0" on BLS and then read the BLD.
(2) To reduce current consumption, set the SVD operation to
OFF unless otherwise necessary.
(3) BLS resides in the same bit at the same address as BLD,
and one or the other is selected by write or read opera-
tion. This means that arithmetic operations (AND, OR,
ADD, SUB and so forth) at this address, pay attention to
whether BLD is ON or OFF.
(4) Select one of the following software processing to return
to the normal mode after a heavy load has been driven in
the heavy load protection mode (S1C6S3L2/6S3B2).
➀
After heavy load drive is completed, return to the
normal mode after at least one second has elapsed.
➁
After heavy load drive is completed, switch BLS ON
and OFF (at least 100 µs is necessary for the ON
status) and then return to the normal mode.
The S1C6S3N2/6S3A2 returns to the normal mode after
driving a heavy load without special software processing.
(5) To reduce current consumption, be careful not to set the
heavy load protection mode with the software unless
otherwise necessary.
(6) When the BLS is to be turned on during operation in the
heavy load protection mode, limit the ON time to 10 msec
per second of operation time.
Summary of Contents for S1C6S3N2
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