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Cisco MGX 8850 Routing Switch Command Reference
Release 2.0, Part Number 78-10467-04 Rev C0, October 2001
Chapter 9
Troubleshooting Commands
dspclksrcs
When you configure a new clock source or the current clock source changes due to any reason, the
software goes through the process of validating the new, current clock source again. (For example, the
reasons other than direct user-configuration can be: the previous clock source goes out of lock or a
resync of the clock sources takes place due to a switch-over or a rebuild.) This validation process takes
the current clock source through the following states:
•
in locking—wideband test
•
in locking—narrowband test
•
locked
During these states, the node is already using the new clock source as the synchronizing source.
You might also see these states—in the sequence previously listed—if the current clock source was
momentarily lost because it drifted out of the lockable range for either the frequency or the phase. In
such a case, the software goes through one more round of trying to confirm that the current clock source
is lockable before it declares a clock source to be unlockable. If the software finds that, even after this
repeated attempt, that the clock source is not coming back within the lockable range, it declares the clock
source as unlockable and proceeds to use the next clock in the hierarchy (of primary, secondary, internal
oscillator) as the current clock source. The exception to this final validation scenario occurs if the current
Table 9-3
Reasons for Change of Clock State
Reason
Meaning
okay
The clock source is okay.
unknown reason
The clock manager has no information for Reason.
no clock signal
Loss of signal (LOS) on the clock source.
frequency too high
The frequency has drifted too high.
frequency too low
The frequency has drifted too low
excessive jitter
Jitter has exceeded tolerance for this stratum.
missing card or component
The active PXM45 has no clock hardware support.
non-existent logical interface The interface is non-existent or not functioning.
interface does not
support clocking
The interface does not support clocking.
phase error
The clock manager has detected a phase error in the clock.
unlockable
The clock manager has attempted to lock the source but found that
the clock signal from this source is unlockable.
out of lock or null
The clock circuitry is again trying to lock a source that went out of
locking range. Note: for Reason, out of lock and null are the same.
reset—not a valid state
The clock source has been reset.
in locking—wideband test
The clock circuitry is in wide bandwidth mode of the locking
process. In this mode, the circuit tests the integrity of the source but
with wide latitude for frequency accuracy. If the source passes this
test, the circuit proceeds to the narrowband test.
in locking—narrow-
band test
The clock circuitry is in narrow bandwidth locking mode. In this
mode, the circuit stringently tests the integrity of the source.
locked
The clock circuitry is locked to this source.
