ARM Musca-S1 Technical Reference Manual Download Page 22

Page: 22 / 194

Major components and systems of the Musca-S1 test chip

SSE-200 subsystem (r1p0)

• Two Cortex-M33 (r0p2) processors with FPU and DSP, and with no coprocessor:

— CPU0: 50MHz. Used as main processor.
— CPU1: 200MHz.

• Memory system:

— One 2KB instruction cache and one 2KB data cache for each Cortex

‑

M33 processor.

— 4×128KB SRAM. One bank, SRAM3, functions as

Tightly Coupled Memory

(TCM),

Tightly Coupled to CPU1 and operating at CPU1 clock speed.

•

Serial Wire Debug

(SWD).

• Secure AMBA interconnect:

— AHB5 Bus matrix.
— AHB5

Exclusive Access Monitors

(EAMs).

— AHB5

Access Control Gates

(ACGs).

— AHB5 to APB bridges.
— Expansion AHB5 master and slave buses - two of each.

• Security components:

— AHB5 TrustZone

Memory Protection Controllers

(MPCs).

— AHB5 TrustZone

Peripheral Protection Controllers

(PPCs).

—

Implementation Defined Attribution Unit

(IDAU).

— CryptoCell-312 (r1p0).
— Secure and Non

‑

secure configurable peripherals and memory access.

— Secure boot.

• Secure APB peripherals:

— One general

‑

purpose timer with configurable security in the

S32KCLK

domain.

— Two CMSDK timers, Timer0 and Timer1 with configurable security, in the

SYSCLK

domain.

— One

Cortex

‑

M System Design Kit

(CMSDK) dual timer with configurable security.

— One secure watchdog in the

S32KCLK

domain.

— One secure watchdog in the

SYSCLK

domain.

— One Non

‑

secure watchdog in the

SYSCLK

domain.

2 Hardware description

2.2 Musca-S1 test chip

101835_0000_01_en

reserved.

2-22

Non-Confidential

Summary of Contents for Musca-S1

Page 2: ...CIAL INCIDENTAL PUNITIVE OR CONSEQUENTIAL DAMAGES HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY ARISING OUT OF ANY USE OF THIS DOCUMENT EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES This document consists solely of commercial items You shall be responsible for ensuring that any use duplication or disclosure of this document complies fully with any relevant export laws ...

Page 3: ...requested Recycle it using local WEEE recycling facilities These facilities are now very common and might provide free collection If purchased directly from Arm Arm provides free collection Please e mail weee arm com for instructions The CE Declaration of Conformity for this product is available on request The system should be powered down when not in use It is recommended that ESD precautions be ...

Page 4: ...are description 2 1 Board hardware 2 18 2 2 Musca S1 test chip 2 20 2 3 Software firmware board and tools setup 2 25 2 4 User components and status LEDs 2 27 2 5 Clocks 2 28 2 6 CryptoCell 312 and One Time Programmable security system 2 32 2 7 Resets and powerup 2 33 2 8 Power 2 34 2 9 I2C interfaces and sensors 2 37 2 10 Arduino Expansion Shield interface 2 38 2 11 Boot memory 2 40 101835_0000_01...

Page 5: ...2 UART control registers 3 171 3 13 GPIO control registers 3 174 3 14 Third party IP 3 176 Appendix A Signal descriptions A 1 Arduino Expansion Shield connectors Appx A 178 A 2 Debug connector Appx A 181 A 3 USB connector Appx A 182 Appendix B Hardware bug software workaround B 1 S1 Secure and Non secure privilege registers hardware bug Appx B 184 Appendix C PVT sensors C 1 PVT sensors Appx C 187 ...

Page 6: ...Arm Musca S1 Test Chip and Board Technical Reference Manual It contains the following About this book on page 7 Feedback on page 10 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 6 Non Confidential ...

Page 7: ... describes the Process Voltage and Temperature PVT sensors on the Musca S1 test chip Appendix D IP configuration This appendix describes the IP configuration of the Musca S1 test chip Appendix E Specifications This appendix contains electrical specifications of the Musca S1 development board Appendix F Revisions This appendix describes the technical changes between released issues of this book Glo...

Page 8: ...abels You must not assume any timing information that is not explicit in the diagrams Shaded bus and signal areas are undefined so the bus or signal can assume any value within the shaded area at that time The actual level is unimportant and does not affect normal operation Clock HIGH to LOW Transient HIGH LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Figure ...

Page 9: ...Clock PL031 Technical Reference Manual DDI 0224 CoreSight Components Technical Reference Manual Arm DDI 0314 Arm DS 5 Arm DSTREAM User Guide Arm DUI 0481 Arm DS 5 Using the Debug Hardware Configuration Utilities Arm DUI 0498 The following confidential books are only available to licensees or require registration with Arm Arm CryptoCell 312 Technical Reference Manual r1p0 100774 Arm v7 M Architectu...

Page 10: ...ata arm com Give The title Arm Musca S1 Test Chip and Board Technical Reference Manual The number 101835_0000_01_en If applicable the page number s to which your comments refer A concise explanation of your comments Arm also welcomes general suggestions for additions and improvements Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader and cannot guarantee the quality of the represented...

Page 11: ...s the following sections 1 1 Precautions on page 1 12 1 2 About the Musca S1 test chip and board on page 1 13 1 3 The Musca S1 development board at a glance on page 1 14 1 4 Getting started on page 1 16 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 1 11 Non Confidential ...

Page 12: ...board has been tested in the temperature range 15 C 30 C 1 1 3 Preventing damage The Musca S1 development board is intended for use within a laboratory or engineering development environment Caution To avoid damage to the Musca S1 development board observe the following precautions Never subject the board to high electrostatic potentials Observe ElectroStatic Discharge ESD precautions when handlin...

Page 13: ...nd systems The Musca S1 development board provides the following main features Musca S1 test chip that includes but is not limited to the following CoreLink SSE 200 subsystem that contains two Arm Cortex M33 r0p2 processors 2MB on chip eMRAM 2MB on chip Code SRAM Peripheral and Arduino Expansion Shield interfaces On board DAPLink that provides the following access Serial Wire or JTAG Debug Port SW...

Page 14: ...Test chip multiplexed I O on page 2 23 3 11 1 IOMUX registers on page 3 122 The following table describes the Musca S1 development board components Table 1 1 Board components Component Comment Musca S1 test chip Samsung Foundry 28FDS eMRAM enabled Internet of Things IoT test chip Boot selector slider switch eMRAM or QSPI Expansion Shield analog I O connector 1V8 or 3V3 I O Selected by jumper link ...

Page 15: ...plies are active Next to nRST button CHRG LED Orange system LED Li ion battery charging in progress Next to ON LED DAP LED Blue system LED DAP activity Next to CHRG LED COM LED Green system LED USB UART activity Next to DAP LED PWR LED Orange system LED Power is connected Next to COM LED RGB user LED Jumper 2 connects red to GPIO 2 and to Expansion Shield digital I O connector 1 17 Jumper 3 connec...

Page 16: ...m actions to boot the development board are as follows 1 Set the boot select switch to QSPI 2 Connect a USB cable to the board 3 Press the PBON button 4 Connect a serial terminal to the USB UART The serial port settings must be 115 2kBaud 8N1 No hardware or software flow control To load a new user image drag and drop the new image onto the drive labeled MUSCA_S 1 Introduction 1 4 Getting started 1...

Page 17: ...ts and status LEDs on page 2 27 2 5 Clocks on page 2 28 2 6 CryptoCell 312 and One Time Programmable security system on page 2 32 2 7 Resets and powerup on page 2 33 2 8 Power on page 2 34 2 9 I2C interfaces and sensors on page 2 37 2 10 Arduino Expansion Shield interface on page 2 38 2 11 Boot memory on page 2 40 2 12 DAPLink controller on page 2 41 2 13 Debug on page 2 42 101835_0000_01_en Copyr...

Page 18: ...3 1V8 3V3 1V8 1V8 3V3 SRAM 2MB Figure 2 1 Hardware infrastructure of the Musca S1 development board Musca S1 development board components and systems The development board contains the following components and systems One Musca S1 test chip with CoreLink SSE 200 Subsystem for Embedded r1p0 The SSE 200 subsystem includes but is not limited to the following CPU0 One Cortex M33 r0p2 processor Floatin...

Page 19: ...nsor I2C interface to test chip On board combined ADC DAC temperature sensor AD5593 6 channel 3V3 ADC DAC GPIO interface to Arduino Shield Temperature indicator Programmable boot select 32MB On board QSPI boot flash 2 1MB on chip boot eMRAM 2MB on chip code SRAM after being preloaded with execution code Both Secure and Non secure access Debug connector that provides access to P JTAG processor debu...

Page 20: ...sors are version r0p2 The test chip also implements a memory subsystem external device interfaces a clock generator and Serial Configuration Control SCC registers for setting default powerup values See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information on the SSE 200 subsystem The following figure shows a high level view of the architecture of the ...

Page 21: ...K CLK1HZ REFCLK CLK32K JTAG SWD S32K WDOG S32K Timer System control Tightly coupled to CPU1 GPIO multiplexer Arduino Shield QSPI memory MPC MPC MPC APB PPC Mux AHB5 to APB APB PPC Mux Dual Timer Timer 0 Timer 1 WDOG Timer 0 WDOG Timer 1 MHU0 MHU1 CryptoCell 312 DAPLink controller Gyro ADC DAC Temperature sensor Security control registers eMRAM 1MB eMRAM 1MB AHB5 to eMRAM QSPI registers Internal SR...

Page 22: ... each Security components AHB5 TrustZone Memory Protection Controllers MPCs AHB5 TrustZone Peripheral Protection Controllers PPCs Implementation Defined Attribution Unit IDAU CryptoCell 312 r1p0 Secure and Non secure configurable peripherals and memory access Secure boot Secure APB peripherals One general purpose timer with configurable security in the S32KCLK domain Two CMSDK timers Timer0 and Ti...

Page 23: ... Code eMRAM External QSPI Flash External powerup reset Three system clock sources External REFCLK 32 768kHz External FASTCLK 32MHz On chip PLL Output up to 200MHz One JTAG SWD debug port One Serial Configuration Controller SCC with dual access port SCC serial during reset accessible by DAPLink only while chip is under powerup reset APB after reset accessible by software or DAPLink while in debug m...

Page 24: ...12 SPIO MISO PA13 GPIO 13 SPIO SCK OUT PA14 GPIO 14 I2C0 Data PA15 GPIO 15 I2C0 Clock GPIO 0 PA16 UART1 RxD Reserved GPIO 1 DAPLink PA17 UART1 TxD GPIO 2 DAPLink PA18 I2C1 Data GPIO 3 Board I2C PA19 I2C1 Clock GPIO 4 Board I2C PA20 QSPI CS1 GPIO 5 QSPI PA21 QSPI IOF0 SCC_LOAD GPIO 6 QSPI PA22 QSPI IOF1 SCC_WNR GPIO 7 QSPI PA23 QSPI IOF2 SCC_DATAIN GPIO 8 QSPI PA24 QSPI IOF3 SCC_CLK GPIO 9 QSPI PA2...

Page 25: ...and hold the ISP button while powering up the board using the USB lead 2 Delete the firmware bin file that appears in the CRP DISABLD USB drive 3 Copy DAPLink_S1_DUAL vxxx bin to the CRP DISABLD drive From a Windows system you can simply Drag and Drop the file On Linux Mac OS use the following command dd if new_firmware bin of Volumes CRP DISABLD firmware bin conv notrunc 4 Power cycle the board u...

Page 26: ... UART setting The default DAPLink UART setting is 115 200 baud 8N1 Related information 1 3 The Musca S1 development board at a glance on page 1 14 2 Hardware description 2 3 Software firmware board and tools setup 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 26 Non Confidential ...

Page 27: ...1V8 power for the Arduino Expansion Shield See 1 3 The Musca S1 development board at a glance on page 1 14 for the location of the jumper links on the board Status LEDs The Musca S1 development board provides the following system status LEDs PWR Orange LED Indicates that power is connected COM Green LED Indicates that USB UART is active DAP Blue LED Indicates DAP activity CHRG Orange LED Indicates...

Page 28: ...Controller SCC interface clock from the DAPLink JTAG TCK Input clock from the debug connector to the CoreSight components on the chip The SCC registers select either 32K or FASTCLK clocks to drive the Musca S1 test chip The default chip driver clock is 32K The driver clock goes to an on chip PLL and divider system The on chip system multiplies the clock frequency to drive the Cortex M33 processors...

Page 29: ... TESTMUX PREMUX REFMUX CPU1 CPU0 DEBUGUGPIKCLK DEBUGSYSCLK BBGEN CG RM38KCLK 0 1 BBGENDIV RM38KMUX CG MRAM_DIV eMRAM SCCCLK DAPSWCLK 32K TCK Figure 2 4 Musca S1 clock system See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for information on the clock system in the SSE 200 subsystem Controlling clock frequencies The SCC registers control the clock system See 3 11...

Page 30: ...CLK for secondary processor CPU1 and SYSCLKDIV derives SYSCLK for primary processor CPU0 The following table shows system control registers FCLK_DIV and SYSCLK_DIV Table 2 3 System control registers FCLK_DIV and SYSCLK_DIV Register Register function Register description FCLK_DIV Controls divider block FCLKDIV in SSE 200 subsystem to derive clock FCLK for secondary processor CPU1 FCLK_DIV Register ...

Page 31: ...hip multiplexed I O on page 2 23 3 11 1 IOMUX registers on page 3 122 Related information 3 11 2 SCC registers summary on page 3 125 2 2 2 Test chip multiplexed I O on page 2 23 3 11 1 IOMUX registers on page 3 122 2 Hardware description 2 5 Clocks 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 31 Non Confidential ...

Page 32: ...y to the CryptoCell 312 The CryptoCell and emulated OTP memory can be used to demonstrate and develop life cycle management key storage and non volatile firmware counters and serves as the Root of Trust RoT for the entire system See 3 10 CryptoCell 312 and One Time Programmable OTP secure memory locations on page 3 121 for the base addresses of the CryptoCell 312 and OTP registers Contact Arm for ...

Page 33: ...rates the reset signal CS_nSRST Reset sequence The following figure shows the reset and powerup timing cycle including Musca S1 test chip and board configuration Power applied Standby Power ON Clock config DAPLink controller reset PBON UART ON Release logic reset Release system reset QSPI boot System running Warm reset SCC config PSUs ON CFG_nRST CB_nRST SCC reset CS_nSRST Figure 2 5 Musca S1 test...

Page 34: ...test chip VDD_PLL1 VDD_CORE VDD_PLL VDD_XTAL AD5593 GPIO Sensors GPIO GPIO Expansion Shield Battery charger USB 5V 1000mA VSS Lithium ion cell optional 3 7V 500mA charging VDD_IO 1V8 LDO 1000mA 1V8 900mA ON SWITCH ON ON 1V8 3V3 I2 C I2 C GPIO FET clamp GPIO 15 0 Pullups GPIO 15 0 BAT USB Shield power supply select Shield IOREF select Board power supply select BAT USB 5V 3V3 IOREF J19 J18 J12 VIN B...

Page 35: ...ned Shield and board current must not exceed the battery current limit VDD_CORE 1V0 150 SoC core supply VDD_IO 1V8 100 SoC I O supply VDD_PLL 1V8 5 PLL VDD low power VDD_XTAL 1V0 1 XTAL VDD External power The DAPLink 5V USB connector supplies all external power to the Musca S1 development board Backup battery A backup battery can power the Musca S1 development board using the connector on the lowe...

Page 36: ...be set to battery power See 1 3 The Musca S1 development board at a glance on page 1 14 for the location of the jumper links Related information 1 3 The Musca S1 development board at a glance on page 1 14 A 3 USB connector on page Appx A 182 2 Hardware description 2 8 Power 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 36 Non Confidential ...

Page 37: ...d Musca S1 test chip Expansion Shield GPIO 15 0 Gyro Sensor MMA7660 AD5593 AN 5 0 ADC I2 C I2 C1 Figure 2 7 I2C interfaces and I2C sensors Note The I2C and GPIO 15 0 signals are on multiplexed Musca S1 test chip I O pins The I O multiplexer must select the correct signals for the required functions to be available See the following for information on how to select the required functions at the Mus...

Page 38: ...O 15 0 IOREF AN 5 0 AREF N C BAT54 5V VIN USB Battery power FET clamp Pullups GPIO 15 0 3V3 GPIO 15 0 1V8 1V8 3V3 Figure 2 8 Arduino Expansion Shield interface The Arduino Shield expansion interface provides Up to 16 1V8 3V3 digital I O I2C I2S SPI UART The UART on the Musca S1 test chip test chip supports hardware flow control 6 channel 3V3 analog from Expansion Shield to the Musca S1 development...

Page 39: ...ca S1 test chip I O The IOMUX registers control the GPIO multiplexer to select the signals at the Musca S1 test chip I O The registers must select the correct signals for the I2C I2S SPI and UART interfaces to be available at the Arduino Expansion Shield See the following for information on how to select the required signals at the Musca S1 test chip I O pins 2 2 2 Test chip multiplexed I O on pag...

Page 40: ...ug Drag and Drop The host computer is connected to the DAPLink interface over USB The DAPLink firmware enables application code to be dropped into either internal eMRAM or external QSPI memory Select the appropriate boot option using the boot selector switch on the board Power cycle the board ON OFF ON and drag and drop the new image The image is automatically programmed to the memory selected by ...

Page 41: ...ass Storage Device USBMSD USB UART and remote reset The DAPLink firmware binary image is available at the Arm Community pages which are accessible from https www arm com musca Note The DAPLink controller is only accessible when P JTAG is disconnected from the debug connector 2 Hardware description 2 12 DAPLink controller 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All right...

Page 42: ...connector Serial Wire or JTAG processor debug SWJ DP available over USB DAPLink Related information 1 3 The Musca S1 development board at a glance on page 1 14 A 2 Debug connector on page Appx A 181 2 Hardware description 2 13 Debug 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 42 Non Confidential ...

Page 43: ...SSE 200 subsystem debug system on page 3 103 3 7 Real Time Clock on page 3 107 3 8 General purpose timer on page 3 108 3 9 PVT sensor registers on page 3 113 3 10 CryptoCell 312 and One Time Programmable OTP secure memory locations on page 3 121 3 11 Serial Configuration Control registers on page 3 122 3 12 UART control registers on page 3 171 3 13 GPIO control registers on page 3 174 3 14 Third p...

Page 44: ...ated in the accompanying text Do not modify undefined register bits Ignore undefined register bits on reads All register bits are reset to a logic 0 by a system or powerup reset All register summary tables in this chapter describe register access types as follows RW Read write RO Read only WO Write only 3 Programmers model 3 1 About this programmers model 101835_0000_01_en Copyright 2019 2020 Arm ...

Page 45: ...age 3 45 3 2 2 Peripheral expansion region memory map on page 3 47 3 2 3 Non secure Expansion 1 region memory map on page 3 48 3 2 4 Secure Expansion 1 region memory map on page 3 49 3 2 5 System region memory map on page 3 50 3 2 6 Complete memory map on page 3 51 3 2 1 Code AHB expansion and SRAM regions memory map The Musca S1 test chip memory map implements the code AHB5 expansion and SRAM reg...

Page 46: ...00 0x3006_0000 0x3008_0000 Reserved 0x0A20_0000 0x1E00_0000 NVM code OTP NS Internal SRAM Bank 1 NS 0x2000_0000 Internal SRAM Bank 0 NS Internal SRAM Bank 3 NS 0x2002_0000 0x2004_0000 0x2006_0000 Internal SRAM Bank 2 NS 0x2008_0000 Reserved 0x0E00_0000 Reserved 0x0E00_2000 NVM code OTP S 0x1000_0000 eMRAM S Reserved External QSPI Flash S Code SRAM S 0x1020_0000 0x1220_0000 0x1A00_0000 0x1A20_0000 ...

Page 47: ...008_3000 0x5008_4000 CMSDK Watchdog on 32KCLK 0x5002_E000 CMSDK Timer on 32KCLK 0x5002_F000 Reserved 0x5003_0000 0x5008_5000 Code AHB5 expansion SRAM Peripheral expansion AHB5 expansion 0 AHB5 expansion 1 System 0x5008_6000 0x0000_0000 0x2000_0000 0x4000_0000 0x6000_0000 0x5008_7000 0x8000_0000 0xE000_0000 0xFFFF_FFFF SSE 200 system memory map CryptoCell 312 0x4008_8000 0x4008_C000 Reserved 0x5008...

Page 48: ...cure SCC registers PWM1 PWM2 0x4010_C000 0x4010_D000 Reserved 0x4010_E000 0x4010_F000 Reserved UART0 UART1 SPI0 I2 C0 I2 C1 I2 S PWM0 Real Time Clock PVT sensors Reserved QSPI registers Timer 0x4010_0000 0x4010_1000 0x4010_2000 0x4010_3000 0x4010_4000 0x4010_5000 0x4010_6000 0x4010_7000 0x4010_8000 0x4010_9000 0x4010_A000 0x4010_B000 GPIO 0x4011_0000 QSPI MPC 0x4012_0000 Reserved 0x4011_1000 Code ...

Page 49: ...CC registers PWM1 PWM2 0x5010_C000 0x5010_D000 Reserved 0x5010_E000 0x5010_F000 Reserved UART0 UART1 SPI0 I2 C0 I2 C1 I2 S PWM0 Real Time Clock PVT sensors Reserved QSPI registers Timer 0x5010_0000 0x5010_1000 0x5010_2000 0x5010_3000 0x5010_4000 0x5010_5000 0x5010_6000 0x5010_7000 0x5010_8000 0x5010_9000 0x5010_A000 0x5010_B000 GPIO 0x5011_0000 QSPI MPC 0x5012_0000 Reserved 0x5011_1000 Code SRAM M...

Page 50: ...Debug ROM for debug element peripherals and expansion region Debug element funnel 0x0000_0000 0x2000_0000 0x4000_0000 0x6000_0000 0x8000_0000 0xE000_0000 0xFFFF_FFFF 0xE000_0000 0xF000_0000 0xF000_2000 SSE 200 system memory map 0xF000_1000 Debug element CTI Reserved 0xF000_3000 Debug APB expansion region 0xF008_0000 Reserved 0xF010_0000 Figure 3 5 Musca S1 test chip memory map System region 3 Prog...

Page 51: ..._0000 0x4000_0FFF 0x5000_0000 0x5000_0FFF 4KB CMSDK Timer 0 CMSDK Timer 0 0x4000_1000 0x4000_1FFF 0x5000_1000 0x5000_1FFF 4KB CMSDK Timer 1 CMSDK Timer 1 0x4000_2000 0x4000_2FFF 0x5000_2000 0x5000_2FFF 4KB CMSDK Dual Timer CMSDK Dual Timer 0x4000_3000 0x4000_3FFF 0x5000_3000 0x5000_3FFF 4KB Message Handling Unit 0 Message Handling Unit 0 0x4000_4000 0x4000_4FFF 0x5000_4000 0x5000_4FFF 4KB Message ...

Page 52: ...B Real Time Clock Real Time Clock 0x4010_9000 0x4010_9FFF 0x5010_9000 0x5010_9FFF 4KB PVT sensors PVT sensors 0x4010_A000 0x4010_AFFF 0x5010_A000 0x5010_AFFF 4KB QSPI registers QSPI registers 0x4010_B000 0x4010_BFFF 0x5010_B000 0x5010_BFFF 4KB General purpose timer General purpose timer 0x4010_C000 0x4010_CFFF 0x5010_C000 0x5010_CFFF 4KB SCC registers SCC registers 0x4010_E000 0x4010_EFFF 0x5010_E...

Page 53: ... secure Secure 0xF000_2000 0xF000_2FFF 4KB Debug element Cross Trigger Interface CTI 0xF008_0000 0xF00F_FFFF 512KB Debug APB expansion region 3 Programmers model 3 2 Memory maps 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 53 Non Confidential ...

Page 54: ...mation on the private processor regions 3 3 2 Instruction cache configuration interface registers The following table shows the instruction cache configuration interface registers Undefined registers are reserved Software must not attempt to access these registers Table 3 2 Instruction cache configuration interface registers Offset Name Type Reset Width Description 0x0000 ICHWPARAMS RO 0x0000_0000...

Page 55: ...pass the cache until the cache invalidation process completes At the end of the cache invalidation process the interrupt status signal IC in the Interrupt Request Status Register ICIRQSTAT is asserted If that interrupt is already enabled or is enabled later an interrupt is raised To enable caching of code fetches you can poll this status register or wait for this interrupt to be raised before cont...

Page 56: ... Enable the instruction cache Cache misses occur when a modification to the Secure Access Unit or the Memory Protection Controller changes the security setting of a recently cached memory region The instruction cache retains the old security attribute and disables hits on the cached line using the new security attribute This situation can result in Secure and Non secure versions of the same memory...

Page 57: ...7 MHU1 CPU0 Interrupt MHU1 CPU1 Interrupt IRQ 8 Reserved IRQ 9 MPC Combined Secure IRQ 10 PPC Combined Secure IRQ 11 MSC Combined Secure IRQ 12 Bridge error combined interrupt Secure IRQ 13 CPU0 instruction cache invalidation interrupt IRQ 14 Reserved IRQ 15 SYS_PPU IRQ 16 CPU0_PPU IRQ 17 CPU1_PPU IRQ 18 CPU0DBG_PPU IRQ 19 CPU1DBG_PPU IRQ 20 Reserved IRQ 21 Reserved IRQ 22 RAM0_PPU IRQ 23 RAM1_PPU...

Page 58: ...r interrupt active HIGH IRQ 44 UARTINTR0 UART0 interrupt active HIGH IRQ 45 UARTRXINTR1 UART1 receive FIFO interrupt active HIGH IRQ 46 UARTTXINTR1 UART1 transmit FIFO interrupt active HIGH IRQ 47 UARTRTINTR1 UART1 receive timeout interrupt active HIGH IRQ 48 UARTMSINTR1 UART1 modem status interrupt active HIGH IRQ 49 UARTEINTR1 UART1 error interrupt active HIGH IRQ 50 UARTINTR1 UART1 interrupt ac...

Page 59: ...ear interrupts and check the written value that raises the interrupts to the cores Set and Clear registers support setting and clearing of individual bits which means the individual bits can represent events that can be independently set and cleared The CPU0 and CPU1 Interrupt Registers are CPU0INTR_STAT Core 0 Interrupt Status Register CPU0INTR_SET Core 0 Interrupt Set Register CPU0INTR_CLR Core ...

Page 60: ...tex M33 processor FCLK can be gated completely during WIC based deep sleep This complete gating is not a standard Cortex M33 processor feature See the Arm Cortex M33 Processor Technical Reference Manual r0p2 for more information on the WIC 3 Programmers model 3 3 Processor elements 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 60 Non Confidential ...

Page 61: ...2 Base peripheral regions The base peripheral regions are where the peripherals of the base element reside There are four regions two Secure and two Non secure See 3 2 2 Peripheral expansion region memory map on page 3 47 and 3 2 6 Complete memory map on page 3 51 The base peripheral regions are 0x4000_0000 to 0x4000_FFFF is a Non secure region 0x4008_0000 to 0x400f_FFFF is a Non secure region 0x5...

Page 62: ...er control registers summary Offset Name Type Reset Width Function 0x0000 CTRL RW 0x0000_0000 32 Bit 3 Interrupt enable Bit 2 Select external input as clock Bit 1 Select external input as enable Bit 0 Enable 0x0004 VALUE RW 0x0000_0000 32 Current value 0x0008 RELOAD RW 0x0000_0020 32 Reload value A write to this register sets the current value 0x000C INSTATUS INTCLEAR RW 0x0000_0020 32 Timer inter...

Page 63: ...he CMSDK dual timer are 0x4000_2000 in the Non secure region 0x5000_2000 in the Secure region The following table shows the dual timer control registers in the Musca S1 test chip in address offset order from the base memory address Undefined registers are reserved Software must not attempt to access these registers See Arm Cortex M System Design Kit Technical Reference Manual for full descriptions...

Page 64: ...OAD RW 0x0000_0000 32 Dual timer 2 background load register 0x0F00 DTIMERITCR RW 0x0000_0000 32 Integration test control register 0x0F04 DTIMERITOP WO 0x0000_0000 32 Integration test output set register Bits 31 2 are reserved 0x0FD0 DTIMERPERIPHID4 RO 0x0000_0004 32 Peripheral ID Register 4 Bits 31 8 are reserved 0x0FE0 DTIMERPERIPHID0 RO 0x0000_0023 32 Peripheral ID Register 0 Bits 31 8 are reser...

Page 65: ...bug subsystem can halt the watchdog timers The timers reside in the PD_SYS power domain and are reset by nWARMRESETSYS The following table shows the watchdog timer control registers in the base element in address offset order from the base memory address Undefined registers are reserved Software must not attempt to access these registers See Arm Cortex M System Design Kit Technical Reference Manua...

Page 66: ...ter 3 Bits 31 8 are reserved 0x0FF0 WDOGPCELLID0 RO 0x0000_000D 8 Component ID Register 0 Bits 31 8 are reserved 0x0FF4 WDOGCELLID1 RO 0x0000_00F0 8 Component ID Register 1 Bits 31 8 are reserved 0x0FF8 WDOGPCELLID2 RO 0x0000_0005 8 Component ID Register 2 Bits 31 8 are reserved 0x0FFC WDOGPCELLID3 RO 0x0000_00B1 8 Component ID Register 3 Bits 31 8 are reserved 3 4 6 Secure Privilege Control Block...

Page 67: ...n how this register is implemented in the Musca S1 test chip 0x0020 SECPPCINTSTAT RO 0x0000_0000 Secure PPC Interrupt Status See SECPPCINTSTAT Register on page 3 70 for information on how this register is implemented in the Musca S1 test chip 0x0024 SECPPCINTCLR WO 0x0000_0000 Secure PPC Interrupt Clear See SECPPCINTCLR Register on page 3 71 for information on how this register is implemented in t...

Page 68: ...page 3 76 for information on how this register is implemented in the Musca S1 test chip 0x0084 APBNSPPCEXP1 RW 0x0000_0000 Expansion 1 Non secure access APB slave Peripheral Protection Control See APBNSPPCEXP1 Register on page 3 77 for information on how this register is implemented in the Musca S1 test chip 0x0090 AHBSPPPC0 RO 0x0000_0000 Secure Unprivileged Access AHB slave Peripheral Protection...

Page 69: ...ID4 RO 0x0000_0004 Peripheral ID 4 0x0FE0 PID0 RO 0x0000_0052 Peripheral ID 0 0x0FE4 PID1 RO 0x0000_00B8 Peripheral ID 1 0x0FE8 PID2 RO 0x0000_000B Peripheral ID 2 0x0FEC PID3 RO 0x0000_0000 Peripheral ID 3 0x0FF0 CID0 RO 0x0000_000D Component ID 0 0x0FF4 CID1 RO 0x0000_00F0 Component ID 1 0x0FF8 CID2 RO 0x0000_0005 Component ID 2 0x0FFC CID3 RO 0x0000_00B1 Component ID 3 SECMPCINTSTATUS Register ...

Page 70: ...Secure Peripheral Protection Controller PPC Interrupt Status Register characteristics are Purpose When access violations occur on any Peripheral Protection Controller a level interrupt is raised from a combined interrupt to the Cortex M33 Nested Vector Interrupt Controller NVIC The PPC Secure PPC Interrupt Status SECPPCINTSTAT Clear SECPPCINTCLR and Enable SECPPCINTEN Registers enable software to ...

Page 71: ...PPCINTCLR Register The Secure Peripheral Protection Controller PPC Interrupt Clear Register characteristics are Purpose When access violations occur on any Peripheral Protection Controller a level interrupt is raised from a combined interrupt to the Cortex M33 Nested Vector Interrupt Controller NVIC The PPC Secure PPC Interrupt Status SECPPCINTSTAT Clear SECPPCINTCLR and Enable SECPPCINTEN Registe...

Page 72: ...r for APB slaves within the memory subsystem 0b0 No effect 0b1 Clear interrupt Reset value 0b0 3 2 Reserved 1 S_APBPPC1PERIP_CLR Interrupt Clear of Peripheral Protection Controller for APB slaves within the system control element 0b0 No effect 0b1 Clear interrupt Reset value 0b0 0 S_APBPPC0PERIP_CLR Interrupt Clear of Peripheral Protection Controller for APB slaves within the base element 0b0 No e...

Page 73: ...et value See 3 4 6 Secure Privilege Control Block on page 3 66 The following table shows the bit assignments of the SECPPCINTEN Register Table 3 13 SECPPCINTEN Register bit assignments Bits Name Function 31 21 Reserved 20 S_AHBPPCGPIO_EN Interrupt Enable of Peripheral Protection Controller for the AHB GPIO slaves 0b0 Mask interrupt 0b1 Enable interrupt Reset value 0b0 19 6 Reserved 5 S_APBPPCSYSP_...

Page 74: ... Manual r1p0 for more information Usage constraints This register is read only Memory offset and full register reset value See 3 4 6 Secure Privilege Control Block on page 3 66 The following table shows the bit assignments of the BRGINTSTAT Register Table 3 14 BRGINTSTAT Register bit assignments Bits Name Function 31 1 Reserved 0 BRG_CPU1SYS_STATUS Interrupt Status of write buffer bridge error for...

Page 75: ...the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information Usage constraints This register is write only Memory offset and full register reset value See 3 4 6 Secure Privilege Control Block on page 3 66 The following table shows the bit assignments of the BRGINTEN Register Table 3 16 BRGINTEN Register bit assignments Bits Name Function 31 1 Reserved 0 BRG_...

Page 76: ...e hardware bugs in the APBSPPPCEXP1 register in the Secure block and in the APBNSPPPCEXP1 register in the Non secure block See B 1 S1 Secure and Non secure privilege registers hardware bug on page Appx B 184 Reset value 0b0 APBNSPPCEXP0 Register The Expansion 0 Non secure Access APB slave Peripheral Protection Control Register characteristics are Purpose Defines the security access settings for th...

Page 77: ...NSPPCEXP1 Register The Expansion 1 Non secure Access APB slave Peripheral Protection Control Register characteristics are Purpose Defines the security access settings for the associated APB slave Peripheral Protection Controllers PPCs outside the SSE 200 subsystem See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information Usage constraints There are no...

Page 78: ...value 0b0 10 NS_GPTIMER Defines the security access setting for the General purpose timer 0b0 Secure access only 0b1 Secure and Non secure access Reset value 0b0 9 NS_QSPI Defines the security access setting for the QSPI 0b0 Secure access only 0b1 Secure and Non secure access Reset value 0b0 8 NS_PVT Defines the security access setting for the PVT sensors 0b0 Secure access only 0b1 Secure and Non ...

Page 79: ...0b0 3 NS_I2C0 Defines the security access setting for the I2C0 interface 0b0 Secure access only 0b1 Secure and Non secure access Reset value 0b0 2 NS_SPI Defines the security access setting for the SPI interface 0b0 Secure access only 0b1 Secure and Non secure access Reset value 0b0 1 NS_UART1 Defines the security access setting for the UART1 0b0 Secure access only 0b1 Secure and Non secure access...

Page 80: ... the GPIO 0b0 Secure privileged access only 0b1 Secure Unprivileged and privileged access Reset value 0b0 0 Reserved AHBSPPPCEXP0 Register The Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control Register characteristics are Purpose Defines the Secure Unprivileged access setting for the associated AHB slave Peripheral Protection Controller PPC outside the SSE 200 subsyste...

Page 81: ...ociated APB slave Peripheral Protection Controllers PPCs for the memory subsystem outside the SSE 200 subsystem See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information Usage constraints There are no usage constraints Memory offset and full register reset value See 3 4 6 Secure Privilege Control Block on page 3 66 The following table shows the bit as...

Page 82: ...e APB PPC Multiplexer outside the SSE 200 subsystem See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information Usage constraints There is a hardware bug in this register See B 1 S1 Secure and Non secure privilege registers hardware bug on page Appx B 184 for the description of the workaround Memory offset and full register reset value See 3 4 6 Secure ...

Page 83: ...ly 0b1 Secure Unprivileged and Privileged access Reset value 0b0 10 S_GPTIMER Defines the Secure access setting for the General purpose timer 0b0 Secure Privileged access only 0b1 Secure Unprivileged and Privileged access Reset value 0b0 9 S_QSPI Defines the Secure access setting for the QSPI 0b0 Secure Privileged access only 0b1 Secure Unprivileged and Privileged access Reset value 0b0 8 S_PVT De...

Page 84: ...access only 0b1 Secure Unprivileged and Privileged access Reset value 0b0 4 S_I2C1 Defines the Secure access setting for I2C1 0b0 Secure Privileged access only 0b1 Secure Unprivileged and Privileged access Reset value 0b0 3 S_I2C0 Defines the Secure access setting for I2C0 0b0 Secure Privileged access only 0b1 Secure Unprivileged and Privileged access Reset value 0b0 2 S_SPI Defines the Secure acc...

Page 85: ... offset order from the base memory address Undefined registers are reserved Software must not attempt to access these registers Table 3 24 Non secure Privilege Control Block registers Offset Name Type Reset value Function 0x00A0 AHBNSPPPCEXP0 RW 0x0000_0000 Expansion 0 Non secure Unprivileged Access AHB slave Peripheral Protection Control Used in SW workaround for hardware bug in another register ...

Page 86: ...0 CID0 RO 0x0000_000D Component ID 0 0x0FF4 CID1 RO 0x0000_00F0 Component ID 1 0x0FF8 CID2 RO 0x0000_0005 Component ID 2 0x0FFC CID3 RO 0x0000_00B1 Component ID 3 AHBNSPPPCEXP0 Register The Expansion 0 Non secure Unprivileged Access AHB slave Peripheral Protection Control Register characteristics are Purpose Defines the Non secure unprivileged access settings for the associated AHB slave Periphera...

Page 87: ... for the associated APB slave Peripheral Protection Controllers PPCs for the memory subsystem outside the SSE 200 subsystem See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information Usage constraints There are no usage constraints Memory offset and full register reset value See 3 4 7 Non secure Privilege Control Block on page 3 85 The following table ...

Page 88: ...lers PPCs outside the SSE 200 subsystem See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 for more information Usage constraints There is a hardware bug in this register See B 1 S1 Secure and Non secure privilege registers hardware bug on page Appx B 184 for the description of the workaround Memory offset and full register reset value See 3 4 7 Non secure Privileg...

Page 89: ...y 1 Non secure Privileged and Unprivileged access Reset value 0b0 10 NS_GPTIMER Defines the Non secure access setting for the General purpose timer 0 Non secure privileged access only 1 Non secure Privileged and Unprivileged access Reset value 0b0 9 NS_QSPI Defines the Non secure access setting for the QSPI 0 Non secure privileged access only 1 Non secure Privileged and Unprivileged access Reset v...

Page 90: ...cess only 1 Non secure Privileged and Unprivileged access Reset value 0b0 4 NS_I2C1 Defines the Non secure access setting for I2C1 0 Non secure privileged access only 1 Non secure Privileged and Unprivileged access Reset value 0b0 3 NS_I2C0 Defines the Non secure access setting for I2C0 0 Non secure privileged access only 1 Non secure Privileged and Unprivileged access Reset value 0b0 2 NS_SPI Def...

Page 91: ...e area in which the MHU resides Only 32 bit writes are supported Byte and halfword writes are ignored See the Arm CoreLink SSE 200 Subsystem for Embedded Technical Reference Manual r1p0 The following table shows the MHU0 and MHU1 registers in address offset order from the base memory address Undefined registers are reserved Software must not attempt to access these registers Table 3 28 MHU registe...

Page 92: ...se element but are shown here for convenience In the Non secure region 0x4012_0000 for QSPI 0x4013_0000 for SRAM 0x4014_0000 for eMRAM In the Secure region 0x5012_0000 for QSPI 0x5013_0000 for SRAM 0x5014_0000 for eMRAM The AHB5 TrustZone MPC gates transactions towards a memory interface when a security violation occurs The security checking is done based on block page level which is configured ex...

Page 93: ...ble 0x001C BLK_LUT n RW 0x0000_0000 Block based gating Look Up Table LUT Access to block based lookup configuration space pointed to by BLK_IDX Bit 31 0 each bit indicates one block If BLK_IDX is 0x0 bit 0 is block 0 bit 31 is block 31 If BLK_IDX is 0x1 bit 0 is block 32 bit 31 is block 63 If BLK_IDX is 0x2 bit 0 is block 64 bit 31 is block 95 If BLK_IDX is 0xFFF bit 0 is block 131040 bit 31 is bl...

Page 94: ..._ns Bit 16 hnonsec Bit 15 0 hmaster Bits are valid when mpc_irq is triggered Subsequent security violating transfers remain blocked that is not captured in this register and the register retains its value until mpc_irq is cleared 0x0034 INT_SET WO 0x0000_0000 Bit 31 1 Reserved Bit 0 mpc_irq set Debug purpose only Sets mpc_irq triggered in INT_STAT regardless of the mpc_irq_enable input 0x0FD0 PIDR...

Page 95: ...ister 4 Read the BLK_LUT register 0xN times to read the complete LUT To write the full contents of the LUT 1 Set autoincrement enable bit CTRL 8 to 0x1 2 Read the BLK_MAX register This register has a value 0xN which represents the last address in the LUT 3 Write 0x0 to the BLK_IDX register 4 Write the new values to the BLK_LUT register 0xN times to fill the complete LUT To read write modify a sing...

Page 96: ...Arm recommends that you write 0x1 to the LUT autoincrement bit CTRL 8 before enabling the configuration lockdown feature When the feature is enabled only LUT reading is available which is simpler when BLK_IDX increments automatically during the read sequence 3 Programmers model 3 4 Base element 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 96 Non Confide...

Page 97: ...O System information registers block S 6 0x5002_1000 0x5002_1FFF 4KB S_SYSCONTROL System control registers block SP 7 0x5002_2000 0x5002_2FFF 4KB SYS_PPU System Power Policy Unit PPU SP 8 0x5002_3000 0x5002_3FFF 4KB CPU0CORE_PPU CPU0 core Power Policy Unit PPU SP 9 0x5002_4000 0x5002_4FFF 4KB CPU0DBG_PPU CPU0 debug Power Policy Unit PPU SP 10 0x5002_5000 0x5002_5FFF 4KB CPU1CORE_PPU CPU1 core Powe...

Page 98: ...e System Information registers in address offset order from the base memory address Undefined registers are reserved Software must not attempt to access these registers Table 3 31 System Information Registers summary Offset Name Access Reset value Description Security 0x000 SYS_VERSION RO 0x2004_1743 System Version Register All 0x004 SYS_CONFIG RO 0x2230_1544 System Hardware Configuration Register...

Page 99: ...0_0000 Fast clock divider configuration 0x0014 SYSCLK_DIV RW 0x0000_0000 System clock divider configuration 0x0018 CLOCK_FORCE RW 0x0000_0000 Clock Force 0x0100 RESET_SYNDROME RW 0x0000_0001 Reset syndrome Register only cleared at powerup reset 0x0104 RESET_MASK RW 0x0000_0030 Reset mask 0x0108 SWRESET WO 0x0000_0000 Software reset 0x010C GRETREG RW 0x0000_0000 General purpose retention 0x0110 INI...

Page 100: ... Component ID3 FCLK_DIV Register The FCLK_DIV Register characteristics are Purpose Controls the divider value of clock divider FCLKDIV that derives FCLK in the SSE 200 subsystem from MAINCLK in the Musca S1 test chip FCLK drives the secondary processor element CPU1 Usage constraints Bits 20 16 are read only Bits 4 0 are read write The other bits are reserved Memory offset and full register reset v...

Page 101: ...llowing table shows the bit assignments Table 3 34 SYSCLK_DIV Register bit assignments Bits Name Function 31 21 Reserved 20 16 SYSCLKDIV_CUR Current value of SYSCLKDIV The division value of SYSCLKDIV divider is SYSCLKDIV_CUR 1 These bits are read only Reset value 0b00011 15 5 Reserved 4 0 SYSCLKDIV Controls SYSCLKDIV division value in SSE 200 subsystem Division value SYSCLKDIV 1 These bits are rea...

Page 102: ... The CMSDK watchdog timer in the system control element is mapped to the secure region only The base memory address is 0x5002_E000 in the secure region The system control element APB Peripherals Protection Controller PPC determines the region in which the timer resides See 3 4 5 CMSDK watchdog timers on page 3 65 for a summary of the CMSDK timer control registers See Arm Cortex M System Design Kit...

Page 103: ...o the debug APB expansion interface The following table shows the memory map that can be accessed by the system APB AP A CoreSight ROM is also expected at address 0xF008_0000 in the debug expansion logic which catalogs all CoreSight expansion debug components outside the subsystem which are are accessible through the debug APB expansion interface Table 3 36 System APB AP address map Row ID Address...

Page 104: ...s by the CPU0 Debug Access Port The following table shows the map for CPU0 when CERTDISABLED is HIGH Table 3 38 CPU0 AHB AP address map when CERTDISABLED is HIGH Row ID Address Size Region name Description From To 1 0x0000_0000 0xF000_7FFF System memory access by the CPU0 Debug Access Port 2 0xF000_8000 0xF000_8FFF 4KB CPU0CSCROM CPU0 access CoreSight ROM 3 0xF000_9000 0xF000_9FFF 4KB CPU0GPR CPU0...

Page 105: ... 0x0000_0000 MEMTYPE register 0xFD0 PIDR4 RO 0x0000_0004 Peripheral ID 4 PIDR4 3 0 JEP106 continuation code which is set by TARGETIDSYS 11 8 0xFE0 PIDR0 RO 0x0000_0043 Peripheral ID 0 PIDR0 7 0 Part number 7 0 which is set by TARGETIDSYS 23 16 0xFE4 PIDR1 RO 0x0000_00B7 Peripheral ID 1 PIDR1 3 0 Part number 11 8 which is set by TARGETIDSYS 27 24 PIDR1 7 4 JEP106 identity code 3 0 which is set by T...

Page 106: ...0000 MEMTYPE register 0xFD0 PIDR4 RO 0x0000_0004 Peripheral ID 4 PIDR4 3 0 JEP106 continuation code 0xFE0 PIDR0 RO 0x0000_0043 Peripheral ID 0 PIDR0 7 0 Part number 7 0 0xFE4 PIDR1 RO 0x0000_00B7 Peripheral ID 1 PIDR1 3 0 Part number 11 8 PIDR1 7 4 JEP106 identity code 3 0 0xFE8 PIDR2 RO 0x0000_000B Peripheral ID 2 PIDR2 2 0 JEP106 identity code 6 4 PIDR2 3 JEDEC identifier PIDR2 7 4 Revision code...

Page 107: ...register 0x000C RTCCR RW 0x0000_0000 32 Control register 0x0010 RTCIMSC RW 0x0000_0000 1 Interrupt mask set and clear register 0x0014 RTCRIS RO 0x0000_0000 1 Raw interrupt status register 0x0018 RTCMIS RO 0x0000_0000 32 Masked interrupt status register 0x001C RTCICR WO 0x0000_0000 32 Interrupt clear register 0x0FE0 RTCPeriphID0 RO 0x0000_0031 8 Peripheral ID register bits 7 0 0x0FE4 RTCPeriphID1 R...

Page 108: ... data value register See 3 8 4 GPTALARM0 Register on page 3 110 0x0014 GPTALARM1 RW 0x0000_0000 1 ALARM1 data value register See 3 8 5 GPTALARM1 Register on page 3 110 0x0018 GPTINTR RO 0x0000_0000 1 Raw interrupt status register See 3 8 6 GPTINTR Register on page 3 111 0x001C GPTCOUNTER RO 0x0000_0000 32 Counter data value register See 3 8 7 GPTCOUNTER Register on page 3 111 This section contains...

Page 109: ...ints Memory offset and full register reset value See 3 8 General purpose timer on page 3 108 The following table shows the bit assignments of the GPTINTM Register Table 3 45 GPTINTM Register bit assignments Bits Name Function 31 2 Reserved 1 0 GPTINTM Current masked status of the interrupt Writing 0b1 enables the ALARM n interrupt 0b0 No effect 0b1 Enable ALARM n interrupt Bit 1 ALARM1 interrupt B...

Page 110: ... value See 3 8 General purpose timer on page 3 108 The following table shows the bit assignments of the GPTALARM0 Register Table 3 47 GPTALARM0 Register bit assignments Bits Name Function 31 0 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value Reset value 0x0000_0000 3 8 5 GPTALARM1 Register The GPTALARM1 Register characteristics are Purpose The ALARM1 data...

Page 111: ...egister bit assignments Bits Name Function 31 1 Reserved 2 0 GPTINTR Raw interrupt state before masking of the GPTINTR interrupt Bit 0 ALARM0 interrupt status Bit 1 ALARM1 interrupt status Bit 2 Or ed ALARM0 and ALARM1 interrupt status Reset value 0b000 3 8 7 GPTCOUNTER Register The GPTCOUNTER Register characteristics are Purpose The counter data value register GPTCOUNTER stores the current 32 bit...

Page 112: ...its Name Function 31 0 GPTCOUNTER Current value of 32 bit timer counter Reset value 0000_0000 3 Programmers model 3 8 General purpose timer 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 112 Non Confidential ...

Page 113: ... Register on page 3 115 0x000C CTRL_CLKSEL RW 0x0000_0000 32 See CTRL_CLKSEL Register on page 3 115 0x0010 CTRL_SAMPLE RW 0x0000_0000 32 See CTRL_SAMPLE Register on page 3 116 0x0014 CTRL_PERIOD RW 0x0000_00FF 32 See CTRL_PERIOD Register on page 3 116 0x0018 OVERFLOW STATUS RO 0x0000_0000 32 See OVERFLOW_STATUS Register on page 3 117 0x001C INTR_STATUS RO 0x0000_0000 32 See INTR_STATUS Register on...

Page 114: ...verflows Reset value 0b0 16 CLEAR_CNTR Clear sensors counters 0b0 No effect 0b1 Clear counters Reset value 0b0 15 4 Reserved 3 CTRL_IRQ_CLEAR Clear PVT interrupt 0b0 No effect 0b1 Clear interrupt Reset value 0b0 2 CTRL_IRQ_EN Enable PVT interrupt 0b0 No effect 0b1 Clear interrupt Reset value 0b0 1 CTRL_AUTORESTART_EN Select operating mode of PVT sensors 0b0 One shot mode 0b1 Repeat mode Reset valu...

Page 115: ...cs are Purpose Individually enables the nine PVT sensors autoclear functions Usage constraints There are no usage constraints Memory offset and full register reset value See 3 9 1 PVT sensor control registers summary on page 3 113 The following table shows the CTRL_AUTOCLEAR Register bit assignments Table 3 54 CTRL_AUTOCLEAR Register bit assignments Bits Name Function 31 3 Reserved 2 0 CTRL_AUTOCL...

Page 116: ...alue See 3 9 1 PVT sensor control registers summary on page 3 113 The following table shows the CTRL_SAMPLE Register bit assignments Table 3 56 CTRL_SAMPLE Register bit assignments Bits Name Function 31 3 Reserved 2 0 CTRL_SAMPLE 2 0 Initiate PVT measurements 0b0 No effect 0b1 Initiate measurement Reset value 0x000 CTRL_PERIOD Register The CTRL_PERIOD Register characteristics are Purpose Stores th...

Page 117: ... assignments Table 3 58 OVERFLOW_STATUS Register bit assignments Bits Name Function 31 3 Reserved 2 0 OVERFLOW_STATUS 2 0 Indicates the PVT sensors overflow status 0b0 No overflow 0b1 Overflow Reset value 0x000 INTR_STATUS Register The INTR_STATUS Register characteristics are Purpose Indicates the reference counter interrupt status Usage constraints This register is read only Memory offset and ful...

Page 118: ...r bit assignments Table 3 60 CLEARED_STATUS Register bit assignments Bits Name Function 31 3 Reserved 2 0 CLEARED_STATUS 2 0 Stores the cleared statuses of the sensors 0b0 Not cleared 0b1 Cleared Reset value 0x000 SAMPLED_STATUS Register The SAMPLED_STATUS Register characteristics are Purpose Individually indicates that PVT measurements are valid Usage constraints This register is read only Memory...

Page 119: ...ame Function 31 0 COUNTER_STATUS Stores the current value of the reference counter Reset value 0x0000_0000 SENSOR0_VAL Register The SENSOR0_VAL Register characteristics are Purpose Stores the value measured by PVT sensor 0 Usage constraints This register is read only Memory offset and full register reset value See 3 9 1 PVT sensor control registers summary on page 3 113 The following table shows t...

Page 120: ...L Register The SENSOR2_VAL Register characteristics are Purpose Stores the value measured by PVT sensor 2 Usage constraints This register is read only Memory offset and full register reset value See 3 9 1 PVT sensor control registers summary on page 3 113 The following table shows the SENSOR2_VAL Register bit assignments Table 3 65 SENSOR2_VAL Register bit assignments Bits Name Function 31 0 SENSO...

Page 121: ...cure region The base memory addresses of the emulated OTP memory are 0x0E00_8000 in the Non secure region 0x1E00_8000 in the Secure region OTP user areas are 0x0E00_0000 in the Non secure region 0x1E00_0000 in the Secure region Contact your Arm representative for information on CryptoCell 312 and the emulated OTP memory Related information 2 6 CryptoCell 312 and One Time Programmable security syst...

Page 122: ...UX registers on page 3 122 3 11 2 SCC registers summary on page 3 125 3 11 1 IOMUX registers The IOMUX registers which are a subset of the SCC register bank control the multiplexer logic that drives Musca S1 test chip I O pins PA26 PA0 The multiplexer controlsMusca S1 test chip I O PA26 PA0 The following figure shows the multiplexer logic 3 Programmers model 3 11 Serial Configuration Control regis...

Page 123: ...UX_MAIN_DEFAULT_IN registers ALTF1 multiplexers Unselected inputs defined by IOMUX_ALTF1_DEFAULT_IN registers ALTF2 multiplexers Unselected inputs defined by IOMUX_ALTF2_DEFAULT_IN registers Figure 3 6 Test chip I O multiplexer logic The IOMUX registers control the IOMUX multiplexer logic The following table shows the IOMUX registers in offset order from the SCC base memory address of 0x4010_C000 ...

Page 124: ...S1 test chip I O PA31 PA0 Routes connection from MAIN input multiplexer to either ALTF1_IN or ALTF2 IOMUX_ALTF1_INSEL Register on page 3 150 0x0890 IOMUX_ALTF1_OUTSEL Controls the Musca S1 test chip I O PA31 PA0 Connects either ALTF1_OUT or ALTF2 to MAIN output multiplexer IOMUX_ALTF1_OUTSEL Register on page 3 151 0x0898 IOMUX_ALTF1_OENSEL Controls the Musca S1 test chip I O PA31 PA0 Connects eith...

Page 125: ...gions of the Expansion 1 region The base memory addresses of the SCC registers are 0x4010_C000 in the Non secure region 0x5010_C000 in the Secure region The following table shows the registers in offset order from the base memory address Undefined registers are reserved Software must not attempt to access these registers Table 3 67 SCC registers summary Offset Name Type Reset Width Description 0x0...

Page 126: ...OUTSEL Register on page 3 148 and 3 11 1 IOMUX registers on page 3 122 0x0878 IOMUX_MAIN_OENSEL RW 0xFFFF_FFFF 32 See IOMUX_MAIN_OENSEL Register on page 3 149 and 3 11 1 IOMUX registers on page 3 122 0x0880 IOMUX_MAIN_DEFAULT_IN RW 0x0000_0000 32 See IOMUX_MAIN_DEFAULT_IN Register on page 3 150 and 3 11 1 IOMUX registers on page 3 122 0x0888 IOMUX_ALTF1_INSEL RW 0x0000_0000 32 See IOMUX_ALTF1_INSE...

Page 127: ...page 3 160 0x099C SCC_MRAM_CTRL1 RW 0x0000_0000 32 See SCC_MRAM_CTRL1 Register on page 3 163 0x09A0 SCC_MRAM_CTRL2 RW 0xFFFF_0119 32 See SCC_MRAM_CTRL2 Register on page 3 163 0x09B0 SCC_MRAM_DIN0 RW 0x0000_0000 32 See SCC_MRAM_DIN0 Register on page 3 164 0x09B4 SCC_MRAM_DIN1 RW 0x0000_0000 32 See SCC_MRAM_DIN1 Register on page 3 165 0x09C0 SCC_MRAM_DOUT0 RO 0x0200_F2CE 32 See SCC_MRAM_DOUT0 Regist...

Page 128: ...s summary on page 3 125 The following table shows the CLK_CTRL_SEL Register bit assignments Table 3 68 CLK_CTRL_SEL Register bit assignments Bits Name Function 31 13 Reserved 12 CTRL_PLL_MUX_CLK_SEL Select PLL MUX input 0b0 PLL0 0b1 Not used Reset value 0b0 3 Programmers model 3 11 Serial Configuration Control registers 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights...

Page 129: ...SWCLK 0b01111 MAINCLK 0b10000 REFCLK 0b10001 CLK1HZ 0b10010 RM38KCLK 0b10101 QSPIPHYCLK 0b10111 PVT_SENSOR_OUT 0b11000 I2SCLK0 0b11001 I2SCLK1 0b11010 I2SCLK2 Undefined settings are reserved Reset value 0b00000 6 SEL_RM38P4_PREMUX_CLK Select RM38KPREMUX input 0b0 SYSSYSSUGCLK 0b1 NRM138P4 not used Reset value 0b1 5 SEL_SCCMUX_CLK Select SCCMUX input 0b0 SCCCLK 0b1 PRE_MUX_CLK Reset value 0b1 3 Pro...

Page 130: ...input 0b0 32K 0b1 FASTCLK Reset value 0b0 Note Multiplexer PLL_MUX is not shown in the clock system diagram in 2 5 Clocks on page 2 28 CLK_PLL_PREDIV_CTRL Register The CLK_PLL_PREDIV_CTRL Register characteristics are Purpose Controls the PLL pre divider division value Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on pa...

Page 131: ...ister bit assignments Table 3 70 CLK_BBGEN_DIV_CLK Register bit assignments Bits Name Function 31 8 Reserved 7 0 BBGEN_DIV 7 0 BBGEN pre divider value Divison value BBGEN_DIV 1 0x00 Minimum divide value 1 no division 0xFF Maximum divide value 1024 Reset value 0x28 CLK_POSTDIV_CTRL_QSPI Register The CLK_POSTDIV_CTRL_QSPI Register characteristics are Purpose Controls the QSPI clock post PLL clock di...

Page 132: ...r bit assignments Table 3 72 CLK_POSTDIV_CTRL_RTC Register bit assignments Bits Name Function 31 0 POSTDIV_CTRL_RTC_DIV 31 0 RTC clock divider division value Divison value POSTDIV_CTRL_RTC_DIV 1 0x0000_0000 Minimum division value 1 no division 0x0000_7FFF Maximum division value 32768 Reset value 0x0000_7FFF CLK_POSTDIV_CTRL_TEST Register The CLK_POSTDIV_CTRL_TEST Register characteristics are Purpo...

Page 133: ...nd full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the CTRL_BYPASS_DIV Register bit assignments Table 3 74 CTRL_BYPASS_DIV Register bit assignments Bits Name Function 31 7 Reserved 6 BYPASS_TEST_DIV_CLK Bypass clock divider TESTDIV 0b0 Not bypass 0b1 Bypass Reset value 0b0 5 Reserved 4 BYPASS_RTC_DIV_CLK Bypass clock divider RTCDIV 0b0 Not bypass ...

Page 134: ...assignments Table 3 75 PLL_CTRL_PLL0_CLK Register bit assignment Bits Name Function 31 15 Reserved 14 12 PLL0_S Controls the output divider that derives the PLL0 output PLL0_CLK from the internal oscillator frequency 0b000 PLL0_CLK INT_OSC 1 0b001 PLL0_CLK INT_OSC 2 0b010 PLL0_CLK INT_OSC 4 0b011 PLL0_CLK INT_OSC 8 0b100 PLL0_CLK INT_OSC 16 0b101 PLL0_CLK INT_OSC 32 0b110 PLL0_CLK INT_OSC 64 0b111...

Page 135: ...its Name Function 31 16 Reserved 15 CTRL_ENABLE_TESTCLK Enable TEST_CLK clock gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 14 CTRL_ENABLE_TAPTCK Enable TCK MUX 0b0 Not enabled 0b1 Enabled Reset value 0b1 13 Reserved 12 CTRL_ENABLE_SCCCLK Enable SCCCLK clock gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 11 CTRL_ENABLE_BBGEN Enable BBGEN clock gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 ...

Page 136: ...ck gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 4 CTRL_ENABLE_I2SCLK1 Enable I2SCLK1 SYSSYSUGCLK clock gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 3 CTRL_ENABLE_I2SCLK0 Enable I2SCLK0 SYSSYSUGCLK clock gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 2 CTRL_ENABLE_GPIOHCLK Enable GPIO SYSSYSUGCLK clock gate 0b0 Not enabled 0b1 Enabled Reset value 0b1 3 Programmers model 3 11 Serial Config...

Page 137: ...y on page 3 125 The following table shows the CLK_STATUS Register bit assignments Table 3 77 CLK_STATUS Register bit assignment Bits Name Function 31 2 Reserved 1 STATUS_LOCK_SIGNAL_PLL0_CLK PLL lock status 0b0 Not locked 0b1 Locked Reset value 0b1 0 STATUS_OUT_CLK_MAINCLK_READY Main clock ready status 0b0 Not ready 0b1 Ready Reset value 0b1 RESET_CTRL Register The RESET_CTRL Register characterist...

Page 138: ...b0 Reset 0b1 No effect Reset value 0b1 15 SSE_200_NRST_SEL Reset SSE 200 subsystem 0b0 Reset 0b1 No effect Reset value 0b1 14 RTC_RESET Reset Real Time Clock 0b0 Reset 0b1 No effect Reset value 0b1 13 PWM2_RESET Reset PWM2 0b0 Reset 0b1 No effect Reset value 0b1 12 PWM1_RESET Reset PWM1 0b0 Reset 0b1 No effect Reset value 0b1 11 PWM0_RESET Reset PWM0 0b0 Reset 0b1 No effect Reset value 0b1 3 Progr...

Page 139: ...ET Reset UART0 0b0 Reset 0b1 No effect Reset value 0b1 6 QSPI_RESET Reset QSPI 0b0 Reset 0b1 No effect Reset value 0b1 5 SPI_RESET Reset SPI 0b0 Reset 0b1 No effect Reset value 0b1 4 I2S_RESET Reset I2S 0b0 Reset 0b1 No effect Reset value 0b1 3 I2C1_RESET Reset I2C1 0b0 Reset 0b1 No effect Reset value 0b1 3 Programmers model 3 11 Serial Configuration Control registers 101835_0000_01_en Copyright 2...

Page 140: ...gister reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the DBG_CTRL Register bit assignments Table 3 79 DBG_CTRL Register bit assignment Bits Name Function 31 DBG_DCU_FORCE SSE 200 debug ports control 0b0 Use Crypto DCU 0b1 Use SCC signals Force Reset value 0b0 30 9 Reserved 8 TODBGENSEL1 Enable or mask bypass Flush input from the Cross Trigger Interface 0b0 En...

Page 141: ...ENIN Non Invasive Debug Enable Input 0b0 Not enabled 0b1 Enabled Reset value 0b1 0 SSE 200 DBGENIN Debug Enable Input 0b0 Not enabled 0b1 Enabled Reset value 0b1 SRAM_CTRL Register The SRAM_CTRL Register characteristics are Purpose Controls SRAM power gate enable signals Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on...

Page 142: ...e 0b0 Not enabled 0b1 Enabled Reset value 0b0 27 CODE_SRAM27_PGEN 28th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 26 CODE_SRAM26_PGEN 27th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 25 CODE_SRAM25_PGEN 26th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 24 CODE_SRAM24_PGEN 25th 64KB SRAM cell power ga...

Page 143: ...enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 19 CODE_SRAM19_PGEN 20th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 18 CODE_SRAM18_PGEN 19th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 17 CODE_SRAM17_PGEN 18th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 16 CODE_SRAM16_PGEN 17th 64KB SRAM cell pow...

Page 144: ...e enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 11 CODE_SRAM11_PGEN 12th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 10 CODE_SRAM10_PGEN 11th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 9 CODE_SRAM9_PGEN 10th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 8 CODE_SRAM8_PGEN 9th 64KB SRAM cell power ...

Page 145: ...enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 3 CODE_SRAM3_PGEN 4th 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 2 CODE_SRAM2_PGEN 3rd 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 1 CODE_SRAM1_PGEN 2nd 64KB SRAM cell power gate enable 0b0 Not enabled 0b1 Enabled Reset value 0b0 0 CODE_SRAM0_PGEN 1st 64KB SRAM cell power gate enab...

Page 146: ..._INIT_VALUE Initial security map at startup for QSPI MPC 0b0 Secure mode 0b1 Non secure mode Reset value 0b0 0 SRAM_MPC_CFG_INIT_VALUE Initial security map at startup for SRAM MPC 0b0 Secure mode 0b1 Non secure mode Reset value 0b0 CPU0_VTOR Register The CPU0_VTOR Register characteristics are Purpose Controls reset vector for CPU0 secure mode Usage constraints There are no usage constraints Memory...

Page 147: ...de eMRAM when BOOT 0b1 Reset value 0x1A00_0000 CPU1_VTOR Register The CPU1_VTOR Register characteristics are Purpose Controls reset vector for CPU1 secure mode Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the CPU1_VTOR Register bit assignments Table 3 84 CPU1_VTOR Register bit a...

Page 148: ...ister reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the IOMUX_MAIN_INSEL Register bit assignments Table 3 86 IOMUX_MAIN_INSEL Register bit assignments Bits Name Function 31 0 IOMUX_MAIN_INSEL 31 0 Main function input data select for Musca S1 test chip multiplexed I O PA31 PA0 0b0 Select ALTF1 0b1 Select MAIN_IN Reset value 0xFFFF_FFFF Note See 2 2 2 Test chip...

Page 149: ...at are available on the multiplexed Musca S1 test chip I O IOMUX_MAIN_OENSEL Register The IOMUX_MAIN_OENSEL Register characteristics are Purpose Selects either MAIN_OE or ALTF1 as output enable signal for Musca S1 test chip I O PA31 PA0 See 3 11 1 IOMUX registers on page 3 122 for information on the Musca S1 test chip I O multiplexer Usage constraints There are no usage constraints Memory offset a...

Page 150: ... multiplexer Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the IOMUX_MAIN_DEFAULT_IN Register bit assignments Table 3 89 IOMUX_MAIN_DEFAULT_IN Register bit assignments Bits Name Function 31 0 IOMUX_MAIN_DEFAULT_IN_0 31 0 Defines value of unselected outputs of ALTF1 input multiple...

Page 151: ...31 PA0 0b0 Select ALTF1_IN 0b1 Select ALTF2 Reset value 0x0000_0000 Note See 2 2 2 Test chip multiplexed I O on page 2 23 for the functions that are available on the multiplexed Musca S1 test chip I O IOMUX_ALTF1_OUTSEL Register The IOMUX_ALTF1_OUTSEL Register characteristics are Purpose Selects either ALTF1_OUT or ALTF2 as output data for Musca S1 test chip I O PA31 PA0 See 3 11 1 IOMUX registers...

Page 152: ...Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the IOMUX_ALTF1_OENSEL Register bit assignments Table 3 92 IOMUX_ALTF1_OENSEL Register bit assignments Bits Name Function 31 0 IOMUX_ALTF1_OENSEL 31 0 I O main function output enable select for Musca S1 test chip multiplexed I O PA31 ...

Page 153: ...to 0b0 0b1 Default to 0b1 Reset value 0x0000_0000 Note See 2 2 2 Test chip multiplexed I O on page 2 23 for the functions that are available on the multiplexed Musca S1 test chip I O IOMUX_ALTF2_INSEL Register The IOMUX_ALTF2_INSEL Register characteristics are Purpose Selects either ALTF2_IN or ALTF3_IN as destination of input signals from ALTF1 input multiplexer for Musca S1 test chip I O PA31 PA...

Page 154: ...st chip I O multiplexer Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the IOMUX_ALTF2_OUTSEL Register bit assignments Table 3 95 IOMUX_ALTF2_OUTSEL Register bit assignments Bits Name Function 31 0 IOMUX_ALTF2_OUTSEL 31 0 Main function output data select for Musca S1 test chip mul...

Page 155: ... 0xFFFF_FFFF Note See 2 2 2 Test chip multiplexed I O on page 2 23 for the functions that are available on the multiplexed Musca S1 test chip I O IOMUX_ALTF2_DEFAULT_IN Register The IOMUX_ALTF2_DEFAULT_IN Register characteristics are Purpose Test chip I O PA31 PA0 Drives unselected outputs of ALTF1 input multiplexers to defined logic levels to prevent floating nodes See 3 11 1 IOMUX registers on p...

Page 156: ...llowing table shows how the bits of the IOPAD_DS0 and IOPAD_DS1 Registers define the drive strengths Table 3 98 Test chip I O drive strengths IOPAD_DS1 DS0_0 Drive strength mA 0b00 2 Default for PA31 PA26 0b01 8 default for PA25 PA20 0b10 4 default for PA19 PA0 0b11 12 Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on p...

Page 157: ...LE Enable pull resistors ofMusca S1 test chip I O PA31 PA0 0b0 Not enabled 0b1 Enabled Reset value 0xFFFF_FFFF IOPAD_PS Register The IOPAD_PS Register characteristics are Purpose Register IOPAD_PS controls the pull resistor modes onMusca S1 test chip I O PA31 PA0 Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 ...

Page 158: ... Register IOPAD_IS controls the input modes on Musca S1 test chip I O PA31 PA0 PA32 Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the IOPAD_IS Register bit assignments Table 3 104 IOPAD_IS Register bit assignments Bits Name Function 31 0 INPUT_SELECT Selects input mode onMusca S1...

Page 159: ...age 3 125 The following table shows the STATIC_CONF_SIG1 Register bit assignments Table 3 106 STATIC_CONF_SIG1 Register bit assignments Bits Name Function 31 28 Reserved 27 24 TODBGENSEL DBGEN mask on CTITRIGOUT 0b0 Mask trigger output of associated Cross Trigger Interface output when DBGEN is LOW 0b1 Not mask trigger output of associated Cross Trigger Interface output Reset value 0b0000 23 16 TIN...

Page 160: ...IN Cross Trigger Interface synchronous bypass on CTITRIGIN Set HIGH to bypass the synchronization logic if the CTITRIGIN input is synchronous with DBGSYSCLK and is driven from the same clock domain 0b0 Not bypass 0b1 Bypass Reset value 0x00 SCC_MRAM_CTRL0 Register The SCC_MRAM_CTRL0 Register characteristics are Purpose Controls the eMRAM memory controller and clock Usage constraints There are no u...

Page 161: ...d Reset value 0b0001 19 16 CSN_HIGH_CLKS Number of clock cycles to wait when CSN is HIGH before going to new access CSN low Reset value 0b0100 15 12 WRITE_CSN_CLKS Number of clock cycles for single write operation Reset value 0b0100 11 PG_VDD18_1 eMRAM1 PG VDD18 0b0 Powered up 0b1 Powered down Reset value 0b0 10 PG_VDD_1 eMRAM1 PG VDD 0b0 Powered up 0b1 Powered down Reset value 0b0 9 PG_VDD18_0 eM...

Page 162: ...le very long wait Reset value 0b00 4 FAST_READ_EN Enable fast read 0b0 Normal read 0b1 Fast read Reset value 0b0 3 MRAM_INV_CLK_SEL Select clock inversion 0b0 Inverted 0b1 Not inverted Reset value 0b0 2 AUTOSTOP_EN Enable autostop 0b0 Disabled 0b1 Enabled Reset value 0b0 1 PROC_SPEC_CLK_EN Enable eMRAM controller clock 0b0 Disabled 0b1 Enabled Reset value 0b1 0 MRAM_CLK_EN Enable eMRAM clock 0b0 D...

Page 163: ...STOP 28 MRAM_RESTB 27 MRAM_LOAD_START 26 MRAM_LOAD_RSTN 25 MRAM_WEN 24 MRAM_CSN Reset value 0b000000 23 0 MRAM_DA_ADDR eMRAM direct access address Reset value 0x00_0000 SCC_MRAM_CTRL2 Register The SCC_MRAM_CTRL2 Register characteristics are Purpose Controls the eMRAM memory direct access Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC reg...

Page 164: ...a 1μS timebase and ensures correct operation of the eMRAM memory and clock If you adjust the eMRAM clock you must adjust PRESCALE to preserve the equality For example if eMRAM clock 15MHz PRESCALE 0x0F 15 eMRAM clock 20MHz PRESCALE 0x14 20 eMRAM clock 30MHz PRESCALE 0x1E 30 Reset value 0x19 25MHz SCC_MRAM_DIN0 Register The SCC_MRAM_DIN0 Register characteristics are Purpose eMRAM data input 31 0 Us...

Page 165: ...MRAM_DOUT0 Register The SCC_MRAM_DOUT0 Register characteristics are Purpose eMRAM memory data output 31 0 Usage constraints This register is read only Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the SCC_MRAM_DOUT0 Register bit assignments Table 3 112 SCC_MRAM_DOUT0 Register bit assignments Bits Name Function 31 0 MRAM_DOUT 31...

Page 166: ...ummary on page 3 125 The following table shows the SCC_MRAM_DOUT2 Register bit assignments Table 3 114 SCC_MRAM_DOUT2 Register bit assignments Bits Name Function 31 0 MRAM_DOUT 77 64 eMRAM memory data output 77 64 These bits store the ECC values automatically added by the eMRAM ECC module Reset value 0x0000_1296 SCC_MRAM_STATUS Register The SCC_MRAM_STATUS Register characteristics are Purpose Stor...

Page 167: ...ROL_REG Register The SELECTION_CONTROL_REG Register characteristics are Purpose Controls clock phase shift control signals Usage constraints There are no usage register read or write constraints Note Arm recommends that you do not alter the default values during normal operation Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the...

Page 168: ...characteristics are Purpose Controls transistor body biasing Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the BBGEN_CTRL Register bit assignments Table 3 117 BBGEN_CTRL Register bit assignments Bits Name Function 31 8 Reserved 7 5 N_CTRL Select VBBN_OUT range 0b001 VBBN_OUT 0 4V...

Page 169: ...BBN 0b1 Body bias enabled BBGen is ON Reset value 0b0 SPARE_CTRL1 Register The SPARE_CTRL1 Register characteristics are Purpose Spare control register Usage constraints There are no usage constraints Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the SPARE_CTRL1 Register bit assignments Table 3 118 SPARE_CTRL1 Register bit assig...

Page 170: ...gister characteristics are Purpose Stores component identification information Usage constraints This register is read only Memory offset and full register reset value See 3 11 2 SCC registers summary on page 3 125 The following table shows the IO_IN_STATUS Register bit assignments Table 3 120 IO_IN_STATUS Register bit assignments Bits Name Function 31 0 IO_IN_STATUS Real time I O pads input statu...

Page 171: ...UART0RSR UART0ECR RW 0x0000_0000 32 Receive Status Register Error Clear Register 0x0018 UART0FR RO 0x0000_0012 32 Flag Register 0x0020 UART0ILPR RW 0x0000_0000 32 IrDA Low Power Counter Register 0x0024 UART0IBRD RW 0x0000_0000 32 Integer Baud Rate Register 0x0028 UART0FBRD RW 0x0000_0000 32 Fractional Baud Rate Register 0x002C UART0LCR_H RW 0x0000_0000 32 Line Control Register 0x0030 UART0CR RW 0x...

Page 172: ...x0000_0000 32 Fractional Baud Rate Register 0x102C UART1LCR_H RW 0x0000_0000 32 Line Control Register 0x1030 UART1CR RW 0x0000_0300 32 Control Register 0x1034 UART1IFLS RW 0x0000_0012 32 Interrupt FIFO Level Select Register 0x1038 UART1IMSC RW 0x0000_0000 32 Interrupt Mask Set Clear Register 0x103C UART1RIS RO 0x0000_0000 32 Raw Interrupt Status Register 0x1040 UART1MIS RO 0x0000_0000 32 Masked In...

Page 173: ... 0x1FF8 UART1PCellID2 RO 0x0000_0005 32 UART1 component ID Register 2 0x1FFC UART1PCellID3 RO 0x0000_00B1 32 UART1 component ID Register 3 3 Programmers model 3 12 UART control registers 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 173 Non Confidential ...

Page 174: ...ue Bits 31 16 are reserved 0x0010 GPIOOUTENSET RW 0x0000_0000 32 Output enable set Bits 31 16 are reserved 0x0014 GPIOOUTENCLR RW 0x0000_0000 32 Output enable clear Bits 31 16 are reserved 0x0020 GPIOINTENSET RW 0x0000_0000 32 Interrupt enable set Bits 31 16 are reserved 0x0024 GPIOINTENCLR RW 0x0000_0000 32 Interrupt enable clear Bits 31 16 are reserved 0x0028 GPIOINTTYPESET RW 0x0000_0000 32 Int...

Page 175: ...er 2 Bits 31 8 are reserved 0x0FEC GPIOPID3 RW 0x0000_0000 32 Peripheral ID Register 3 Bits 31 8 are reserved 0x0FF0 GPIOCID0 RW 0x0000_0000 32 Component ID Register 0 Bits 31 8 are reserved 0x0FF4 GPIOCID1 RW 0x0000_0000 32 Component ID Register 1 Bits 31 8 are reserved 0x0FF8 GPIOCID2 RW 0x0000_0000 32 Component ID Register 2 Bits 31 8 are reserved 0x0FFC GPIOCID3 RW 0x0000_0000 32 Component ID ...

Page 176: ...he Non secure region Base memory address 0x5010_6000 in the Secure region Pulse Width Modulator IP IP6512 PWM0 Base memory address 0x4010_7000 in the Non secure region PWM0 Base memory address 0x5010_7000 in the Secure region PWM1 Base memory address 0x4010_E000 in the Non secure region PWM1 Base memory address 0x5010_E000 in the Secure region PWM2 Base memory address 0x4010_F000 in the Non secure...

Page 177: ...rface connectors It contains the following sections A 1 Arduino Expansion Shield connectors on page Appx A 178 A 2 Debug connector on page Appx A 181 A 3 USB connector on page Appx A 182 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx A 177 Non Confidential ...

Page 178: ...oltage reference connector Musca S1 board Figure A 1 Arduino Shield interface connectors Digital I O connectors J11 J15 Connector J11 provides Shield digital I O GPIO 15 8 and connector J15 provides Shield digital I O GPIO 7 0 Connector J11 also provides the analog I O reference voltage The IOMUX registers select one of the Shield interface GPIO pin functions sets ALTF1 ALTF2 or ALTF3 The IOMUX re...

Page 179: ...n Primary reset or powerup ALTF1 ALTF2 ALTF3 1 GPIO 0 UART0 RxD Reserved Reserved 2 GPIO 1 UART0 TxD 3 GPIO 2 MR_I2S_SD PWM0 4 GPIO 3 MR_I2S_WS PWM1 5 GPIO 4 MR_I2S_SCK PWM2 6 GPIO 5 MT_I2S_SD0 UART0_CTS 7 GPIO 6 MT_I2S_WS0 UART0_RTS 8 GPIO 7 MT_I2S_SD1 UART1_CTS Shield analog I O connector J14 Connector J14 provides six analog I O for the Arduino Expansion Shield The following table shows the pin...

Page 180: ...for connector J13 Table A 4 Shield power and voltage reference connector J13 signal list Pin Signal 1 N C 2 IOREF 3 N C 4 3V3 5 5V 6 GND 7 GND 8 VIN Related information 1 3 The Musca S1 development board at a glance on page 1 14 2 10 Arduino Expansion Shield interface on page 2 38 A Signal descriptions A 1 Arduino Expansion Shield connectors 101835_0000_01_en Copyright 2019 2020 Arm Limited or its...

Page 181: ... Debug connector The following table shows the pin mapping for the debug connector Table A 5 Debug connector pin mapping Pin Signal Pin Signal 1 3V3 2 SWDIO TMS 3 GND 4 SWDCLK TCK 5 GND 6 SWO TDO 7 N C 8 NC TDI 9 GNDDETECT 10 nSRST Note Pins 2 4 6 8 9 and 10 have pullup resistors to 3V3 Related information 1 3 The Musca S1 development board at a glance on page 1 14 2 13 Debug on page 2 42 A Signal...

Page 182: ...ctor The following table shows the pin mapping of the mini B USB connector Table A 6 Mini B USB connector Pin Signal Pin Signal 1 5V 2 DATA 3 DATA 4 ID 5 GND 6 GND_EARTH Note The GND_EARTH connection is the casing of the mini B connector Related information 1 3 The Musca S1 development board at a glance on page 1 14 2 8 Power on page 2 34 A Signal descriptions A 3 USB connector 101835_0000_01_en C...

Page 183: ...or hardware bugs in Secure and Non secure privilege registers It contains the following section B 1 S1 Secure and Non secure privilege registers hardware bug on page Appx B 184 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx B 183 Non Confidential ...

Page 184: ...ock offset 0x60 AHBSPPPCEXP0 Secure Privilege block offset 0xA0 AHBNSPPPCEXP0 Non secure Privilege block offset 0xA0 Secure access When Secure access is selected that is APBNSPPCEXP1 n 0b0 for a peripheral the following table describes The intended Privileged and Unprivileged access settings for the settings in register APBSPPPCEXP1 The effects of the hardware bug in register APBSPPPCEXP1 The soft...

Page 185: ...ecurity setting APBNSPPPCEXP1 n Non secure privilege block offset 0xC4 Intended Privileged and Unprivileged access settings for selected peripheral Effect of hardware bug Software workaround Bit n 0b1 Non secure access Bit n 0b0 Privileged access only Works correctly Bit n 0b1 Unprivileged and Privileged access Incorrect operation Cannot select Unprivileged access Write to the following registers ...

Page 186: ...rocess Voltage and Temperature PVT sensors on the Musca S1 test chip It contains the following section C 1 PVT sensors on page Appx C 187 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx C 186 Non Confidential ...

Page 187: ... 1 1 0 Counter 1 Resync PVT sensor 1 Figure C 1 PVT sensors and system The PVT sensor system has the following main features Polling of the sensor outputs by regularly checking the status flags Event mode where the REF counter interrupt signal indicates that PVT measurements are ready Synchronized start and enable One shot mode or repeat mode Each sensor is controllable independently of the others...

Page 188: ...ate that a new measurement value is ready Overflow to indicate that the sensor counter has reached 0xFFFF_FFFF The overflow flag stays HIGH until the reference counter initiates a new measurement Ring oscillators The ring oscillators consist of 501 inverting stages and the PVT sensor control registers can enable or disable them The ring oscillators are built from different inverting cells NOT NAND...

Page 189: ...escribes the IP configuration of the Musca S1 test chip It contains the following section D 1 IP configuration on page Appx D 190 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx D 189 Non Confidential ...

Page 190: ...M0 System Design Kit r1p0 00rel0 BP300 BU 50000 Arm CoreLink SIE 200 System IP for Embedded r3p1 00rel0 PL408 BU 50000 Arm CoreLink LPD 500 Low Power Interface Distributor r0p0 00rel0 TM100 BU 50000 Arm CoreSight SoC 400 r3p2 50rel1 TM976 BU 50000 Arm CoreSight ETM M33 r0p2 00rel0 AT624 MN 22110 Arm Cortex M33 FPU r0p2 00rel0 BP210 BU 00000 Arm Cortex M System Design Kit r1p0 01rel0 CC010 BU 50000...

Page 191: ...trical specifications of the Musca S1 development board It contains the following section E 1 Electrical specifications on page Appx E 192 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx E 191 Non Confidential ...

Page 192: ...e as follows See 2 8 Power on page 2 34 for information on the Musca S1 development board power supply rails and maximum current loads E Specifications E 1 Electrical specifications 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx E 192 Non Confidential ...

Page 193: ...es the technical changes between released issues of this book It contains the following section F 1 Revisions on page Appx F 194 101835_0000_01_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx F 193 Non Confidential ...

Page 194: ...e and Non secure privilege registers hardware bug on page Appx B 184 All board versions Added explanatory text in registers affected by the hardware bug APBSPPPCEXP1 Register on page 3 82 APBNSPPPCEXP1 Register on page 3 88 All board versions Added explanatory text and bit description for bit 0 in registers used in the software workaround for the software bug AHBNSPPCEXP0 Register on page 3 75 AHB...

Search results

Summary of Contents for Musca-S1

Reviews:

Related manuals for Musca-S1

Brands by name

Popular brands

ARM Musca-S1, Technical Reference Manual

Search results

Summary of Contents for Musca-S1

Reviews:

Related manuals for Musca-S1

Brands by name

Popular brands