The address map for CPU0 depends on the value of CERTDISABLED.
Note
CERTDISABLE, CERTDISABLED, CERTREADEN, and CERTREADENABLED are indicated by the
register SCSECCTRL. See
3.5.3 System Control Register Block
Arm
®
CoreLink
™
SSE
‑
200 Subsystem for Embedded Technical Reference Manual (r1p0)
.
The following table shows the map for CPU0 when CERTDISABLED is LOW.
Table 3-37 CPU0 AHB-AP address map when CERTDISABLED is LOW
Row ID Address
Size Region name Description
From
To
1
0x0000_0000 0x2FFF_FFFF
-
-
System memory access by the CPU0 Debug Access Port.
2
0x3000_0000 0x3000_1FFF
8KB CERTMEM
Certificate Access Memory region, residing in SRAM0. Write
access is allowed and read data is masked to zero if
CERTREADENABLED is LOW. Access bypasses the processor
core.
3
0x3000_2000 0xF000_7FFF
-
-
System memory access by the CPU0 Debug Access Port.
2
0xF000_8000 0xF000_8FFF
4KB CPU0CSROM CPU0 Access CoreSight ROM.
3
0xF000_9000 0xF000_9FFF
4KB CPU0GPR
CPU0
Granular Power Requester
(GPR)
4
0xF000_A000 0xFFFF_FFFF
-
-
System memory access by the CPU0 Debug Access Port.
The following table shows the map for CPU0 when CERTDISABLED is HIGH.
Table 3-38 CPU0 AHB-AP address map when CERTDISABLED is HIGH
Row ID Address
Size Region name Description
From
To
1
0x0000_0000 0xF000_7FFF
-
-
System memory access by the CPU0 Debug Access Port.
2
0xF000_8000 0xF000_8FFF
4KB CPU0CSCROM CPU0 access CoreSight ROM.
3
0xF000_9000 0xF000_9FFF
4KB CPU0GPR
CPU0
Granular Power Requester
(GPR).
4
0xF000_A000 0xFFFF_FFFF
-
-
System memory access by the CPU0 Debug Access Port.
CPU1 AHB-AP is for CPU1, secondary core, debug access. It also maps a CoreSight ROM and a
Granular Power Requester
(GPR).
The following table shows the memory map for CPU1 AHB-AP.
Table 3-39 CPU1 AHB-AP address map
Row ID Address
Size Region name Description
From
To
1
0x0000_0000 0xF000_7FFF
-
-
System memory access by the CPU1 Debug Access Port.
2
0xF000_8000 0xF000_8FFF
4KB CPU1SCROM CPU1 Access CoreSight ROM.
3
0xF000_9000 0xF000_9FFF
4KB CPU1GPR
CPU1
Granular Power Requester
(GPR).
4
0xF000_A000 0xFFFF_FFFF
-
-
System memory access by the CPU1 Debug Access Port.
3 Programmers model
3.6 SSE-200 subsystem debug system
101835_0000_01_en
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