Arbiter Systems 1088A, Operation Manual

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158 Options List
Output Signal Enable and Configuration
When jumper JMP17 on the main clock board is set properly, the digital outputs of that clock
are controlled by the redundant-control interface. The status of the drivers is indicated by the
’On Line’ LED annunciator on the clock front panel. Refer to paragraphs 3.2 through 3.3.4 of the
1088B Operation manual if it should be necessary to modify the jumper settings; they are normally
preset at the factory prior to shipment.
To make the best use of the redundant clock feature, both clocks should have their main four outputs
set for the same set of signals. Then, the outputs may be directly tied in parallel, and the ’On Line’
clock will drive the connected loads. Note that the output enable only affects the digital outputs
(everything except IRIG-B modulated and chart recorder output).
If you connect two analog
outputs together, no damage will be done, but both signals will be present simultaneously. The
IRIG bus distribution output of the Option 18 assembly should be used for a redundant modulated
IRIG-B output; it includes an on-line enable relay, which is also controlled by the output enable
function.
On-Line Control and Arbitration
In normal operation, when no fault is detected, the ’On Line’ clock is determined by the ’luck of
the draw.’ The only exception to this is if one of the clocks includes a higher-stability internal
timebase, such as Option 12. In this case, the clock with the higher-quality timebase will be the
nominal on-line clock.
Once each second, the clocks exchange status information via the RS-232 interface. In the event that
one of the clocks determines that it is not as healthy as the other, it will automatically relinquish
on-line status to the other unit. For the most part, this is performed in firmware; however, there
is also a hardware input to the redundant-control circuit, which is driven by the microprocessor
watchdog/reset generator. If this circuit detects any error, a direct hardware transfer to the other
unit is performed. Thus, in the event of a processor failure which might prevent the clock from
relinquishing on-line status via firmware, the transfer will be accomplished automatically through
this hardware feature.
Determination of the on-line clock in the event of multiple failures is made by comparison of the
status bytes (refer to paragraph 4.4 for a discussion of clock status). The clock with the lower-
valued status byte will be elected to on-line status. The status of both clocks may be monitored
from either of the clocks via the SS RS-232 command; see Appendix A of the 1088B Operation
manual for a description.
Use With Other Options
Certain other options, including Options 03 and 20, can be installed in the clock mainframe along
with the Option 18 board, and also can provide redundant control of their outputs via the redundant
clock control function of the Option 18 assembly. See the documentation for these options to
determine if any jumper settings are required to take advantage of this feature.
C.14.8 Option 18 Setup
The setup menu to control the operation of the Option 18 interface is shown earlier in this section
(Option 18 Firmware Setup). No internal configuration is necessary for proper operation of the