Abov MC96FM204, User Manual

Page: 118 / 172

MC96FM204/FM214
118 April 7, 2016 Ver. 1.8
SPISR (SPI Status Register) : C0H
7 6 5 4 3 2 1 0
SPIIFR WCOL SS_HIGH
–
FXCH SSENA
– –
R/W R R/W
–
R/W R/W
– –
Initial value : 00H
SPIIFR
When SPI Interrupt occurs, this bit becomes
‘1’. IF SPI interrupt is
enable, this bit is auto cleared by INT_ACK signal. And if SPI Interrupt
is disable, this bit is cleared when the status register SPISR is read, and
then access (read/write) the data register SPIDR
0 SPI Interrupt no generation
1 SPI Interrupt generation
WCOL
This bit is set if any data are written to the data register SPIDR during
transfer. This bit is cleared when the status register SPISR is read, and
then access (read/write) the data register SPIDR.
0 No collision
1 Collision
SS_HIGH When the SS pin is configured as input, if
“HIGH” signal comes into the
pin, this flag bit will be set.
0
Cleared when ‘0’ is written
1
No effect when ‘1’ is written
FXCH SPI port function exchange control bit.
0 No effect
1 Exchange MOSI and MISO function
SSENA
This bit controls the SS pin operation
0 Disable
1 Enable (The P01 should be a normal input)