The pulse width modulation is controlled by the internal gate (I gate). The I gate is iden-
tical to the software gate (SW gate).
SW gate:
open (activate): In the user program by setting
SW_EN
of SFB 49
close (deactivate): In the user program by resetting
SW_EN
of SFB 49
If values during the PWM output are changed, the new values will be
issued until the beginning of a new period. A just started period runs
always to the end!
5.8.5 Parametrization
5.8.5.1
Address assignment
Sub module
Input address
Access
Assignment
Counter
816
DINT
Channel 0: Counter value / Frequency value
820
DINT
Channel 1: Counter value / Frequency value
824
DINT
Channel 2: Counter value / Frequency value
828
DINT
Channel 3: Counter value / Frequency value
Sub module
Output address
Access
Assignment
Counter
816
DWORD
reserved
820
DWORD
reserved
824
DWORD
reserved
828
DWORD
reserved
5.8.5.2
Operating mode per channel
Select via
‘Channel’
the channel select via
‘Operating’
the operating mode. The fol-
lowing operating modes are supported:
n
Not parameterized: Channel is deactivated
n
Chapter 5.6.6.1 ‘Count continuously’ on page 115
n
Chapter 5.6.6.2 ‘Count once’ on page 116
n
Chapter 5.6.6.3 ‘Count Periodically’ on page 119
n
Chapter 5.7 ‘Frequency measurement’ on page 128
n
Chapter 5.8 ‘Pulse width modulation - PWM’ on page 137
Depending on the selected operating mode default values are loaded and shown in an
additional register.
Controlling PWM
Parameter hardware con-
figuration
VIPA System SLIO
Deployment I/O periphery
Pulse width modulation - PWM > Parametrization
HB300 | CPU | 013-CCF0R00 | en | 16-40
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