C H A P T E R 3 C O N F I G U R I N G V 1 0 0
V100 Versatile Multiplexer Technical Manual Version 2.2
Page 69 of 231
Field Options Description
CHANNEL
Information only
Displays the numbers of all data channels
installed in the unit on a separate line.
INTERFACE
V.11, V.24, V.35, RS449 Electrical interface standard used on the port.
Agg,
Channel is used as an Aggregate
Trib,
Channel is a tributary
MODE
TDM
Channel is a tributary, multiplexed through TDM
port
DTE,
Port is configured as Data Terminating Equipment
(TX is an output)
TYPE
DCE
Port is configured as Data Communications
Equipment (TX is input)
Sync,
Data is transparent synchronous
NRZ,
Data is synchronous, HDLC Non-Return to Zero
format
NRZI,
Data is synchronous, HDLC Non-Return to Zero
Inverted format
8N1,
Data is async, 8bits, no parity, one stop
8N2,
Data is async, 8bits, no parity, two stop
7E1,
Data is async, 7bits, even parity, one stop
7E2,
Data is async, 7bits, even parity, two stop
7O1,
Data is async, 7bits, odd parity, one stop
7O2,
Data is async, 7bits, odd parity, two stop
7N1,
Data is async, 7bits, no parity, one stop
7N1.5,
Data is async, 7bits, no parity, 1.5 stop
5N1,
Data is async, 5bits, no parity, one stop
FORMAT
5N1.5
Data is async, 5bits, no parity, 1.5 stop
R,
Raw data passed transparently
E, Error-correction
active
FORMAT (ASYNC)
C
Compression active (error-correction is
automatic)
Receive clock bit rate. This may be set at any
rate from
50 to 2048000bps (synchronous) or
RX CLOCK RATE
50-2048000bps
50 to 115200bps (asynchronous)
Ext,
RX clock input from the interface
Txc,
RX clock output, looped from TX
PLL,
RX clock output, derived from PLL
Int,
RX clock output, phase-locked from system clock
RX CLOCK SOURCE
Dba
Dynamic Bandwidth Allocation (output)
- None
RX CLOCK
REFERENCE
<GTX,
The reference for the TX PLL is taken from the
Global RX Clock bus
<GRX
The reference for the RX PLL is taken from the
Global RX Clock bus
