C H A P T E R 4 F E A T U R E S
V100 Versatile Multiplexer Technical Manual Version 2.2
Page 147 of 231
clock speeds on all DBA ports whenever a change occurs in the DBA pool. The rate-change calculations
are performed at both ends of the connection, with the overall size of the dynamic bandwidth pool limited
by the lowest link bit rate across the network.
Asynchronous channels are treated in a similar way, where the configured channel bit rate again defines
the proportion of the DBA pool allocated, but this time to the internal connection between the two ends,
since the local connection speed out of the port must be set as configured. One extra feature takes
advantage of the bursty nature of async data: when data stops, the internal connection speed drops to a
nominal 2400bps (or the port speed, whichever is the lower) to maintain the connection ready for use
while returning most of the bandwidth to the DBA pool. When the next data character is received by the
port, the internal connection rate resumes its normal DBA level. In this way the V100 maximises
bandwidth use automatically, without the user having to intervene or precalculate any bit rates.
At all times the V100 optimises buffering and delay so as to maintain voice quality and efficient data
transfer. Packet lengths are constantly adapted to match the varying traffic demands of all channel types.
4.6
Asymmetric Bandwidth
The V100 is capable of considerable flexibility in clocking schemes and may operate RX and TX clock
independently and at different rates.
Each direction has an associated Phase-Locked Loop (PLL) which may use as it reference the input clock,
either Global clock (GRX or GTX) or the internal system clock. Each PLL is then capable of generating an
output clock at any rate from 1600bps up to 2Mbps in steps of 800Hz. Below 1600bps, any multiple of
25bps from 50bps upwards may be generated.
