Parameter Description VD500 Series Inverter User Manual
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30
Accumulative
running time reached
When frequency inverter accumulative running time more than
the setting time of Fb-35, output ON signal.
31
Accumulative
power-on time
reached
When frequency inverter accumulative power-on time more
than the setting time of Fb-35, output ON signal.
32
Timing reached
outpu
When timing function selection (Fb-36) is valid, afrer inverter
running time reach to set timing time, output ON signal.
33
PLC circulation
output
When simple PLC operation to finished a cycle, output a pulse
signal whit 250ms width.
34
Frequency limit
When set frequency exceed frequency upper limit or frequency
lower limit, and the inverter output frequency reaches frequency
upper limit or frequency lower limit, output ON signal.
35
Torque limit
Inverter in speed control mode, when output torque reaches the
torque limit value, the inverter in the stall protection state,
output ON signal at the same time time.
36
Reverse running
When frequency inverter in reverse running, output ON signal.
37
AI1 input limit
When the value of analog input AI1 is more than Fb-41 (AI1
input protection upper limit) or less than Fb-40 (AI1 input
protection lower limit), output ON signal.
38
AI1>AI2
When the value of analog input AI1 is more than the input value
of AI2, output ON signal.
39
Communication
setting
Please refer to the communication protocol.
41
Timing braking
(power on braking)
Please refer to the instruction of function code Fb-48, Fb-49.
42
Inverter in running
(jog no output)
Said the inverter is in running state, have the output frequency
(can be zero), except jog, then output ON signal.
F6-06
DO Output Terminal
Effective State Selection
Unit’s digit: HDO1
0: Positive logic
1: Oppositive logic
Ten’s digit: RELAY1, same as above
Hundred’s digit: RELAY 2, same as
above
Thousand’s digit: DO1, same as above
Ten thousand’s digit: DO5 (expansion
card), same as above
0x00000
○
Define HDO1 (digital output), relay 1, relay 2 and DO1 and DO5 (expansion card) output logic.
0: Positive logic, digital output terminal and the corresponding piplic end connected to valid state,
disconnect as invalid state;
1: Anti-logic, digital output terminal and the corresponding public end connected as the invalid state,
disconnect for valid state.
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