Toshiba TMPR7901, Руководство пользователя

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Chapter 6: SDRAM Memory Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
6-10
Field Bit(s) Description
Timing
Symbol
RRT 28:26
Refresh Recovery Time (110)
These bits specify the earliest timing for a new command
after a Refresh command.
001 : 5 clock cycles
010 : 6 clock cycles
011 : 7 clock cycles
100 : 8 clock cycles
101 : 9 clock cycles
110 : 10 clock cycles
111 : 16 clock cycles
000 : Reserved
tRFC
A2P 29
Activate to Precharge (1)
This bit specifies the earliest timing for a PRECHARGE
command after an ACTIVE command.
0 : 5 clock cycles
1 : 6 clock cycles
tRAS
– 31:30 Reserved –
The following figure shows example timing parameters.
Figure 6-6 Example Timing Parameters
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
≥
tRAS
ACTIVE
READ PRE
tCAS
ROW COL
Read data Read data
ACTIVE WRITE
Any
command
tRCD
≥
tRAS
ROW COL
≥
tWR
Write
data
Write
data
REFRESH
Any
command
≥
tRFC
COMMAND
Address
DQ
COMMAND
Address
DQ
tRCD
COMMAND
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Any
command
tPR