Toshiba TMPR7901, Руководство пользователя

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Chapter 6: SDRAM Memory Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
6-26
| 0 << 15 /* 3 15 Burst Type = Sequential */\
| 3 << 16 /* 6:4 18:16 CAS Latency = 3 */\
| 0 << 19 /* 8:7 20:19 OpMode = Standard Op */\
| 0 << 21 /* 9 21 Write Burst Mode = programmed */\
| 0xa000_0000 /* UnCached UnMapped area for DIMM0 */
#define SDR_RFSH /* Refresh Register's value */\
1500 /* RIC: 64ms/4096 >15,000 ns @ 100 MHz */\
| 0<<16 /* NSRF: Staggered refresh */\
| 1<<17 /* RFE: Refresh enable */\
# initialize registers and force NOP mode
la k1, SDRAMC # SDRAMC base address
la t1, DIMM0ADDR # address of dummy write for DIMM0
li t0, DOMR_NOP
sq t0, DOMR(k1) # force NOP mode to prevent unnecessary access
# specify SDRAM parameter
li t0, DPR_CL3
sq t0, D0PR(k1)
sq t0, D1PR(k1)
sq t0, D2PR(k1)
sq t0, D3PR(k1)
# set up SDRAM address windows
li t0, RAMBASE # start address of DIMM0
li t2, R RAM 32MB-1
# end address of DIMM0
sq t0, D0LOW(k1) # store DIMM0 LOW reg (starting 0x0000_0000)
sq t2, D0HIGH(k1) # store DIMM0 HIGH reg (32MB)
li t0, R RAM32MB
li t2, R RAM32MB*2-1
sq t0, D1LOW(k1) # store DIMM1 LOW reg (starting 0x0200_0000)
sq t2, D1HIGH(k1) # store DIMM1 HIGH reg (0MB)
li t0, R RAM32MB*2
li t2, R RAM32MB*3-1
sq t0, D2LOW(k1) # store DIMM2 LOW reg (starting 0x0400_0000)
sq t2, D2HIGH(k1) # store DIMM2 HIGH reg (0MB)
li t0, R RAM32MB*3
li t2, R RAM32MB*4-1
sq t0, D3LOW(k1) # store DIMM3 LOW reg (starting 0x0600_0000)
sq t2, D3HIGH(k1) # store DIMM3 HIGH reg (0MB)
#Precharge All Bank
li t0, DOMR_PRECHARGE
sq t0, DOMR(k1) # mode set to precharge all bank
sw $0, 0(t1) # issue command
# two Auto Refresh cycles
li t0, DOMR_REFRESH
sq t0, DOMR(k1)
sw $0, 0(t1) # issue command
sw $0, 0(t1) # issue command twice