Toshiba TMPR7901, Руководство пользователя

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Chapter 2: Features
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
2-2
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PCI/G-Bus Bridge (“PGB”)
•
Fully compliant with PCI Local Bus Specification Rev. 2.1
•
32-bit PCI bus interface
•
33 MHz or 66 MHz PCI operation
•
Zero-Latency Back to Back transfers
•
Supports on-chip arbitration of up to 5 masters (supports a maximum of 2 - 4
external PCI devices)
•
Dual Address cycle
•
Supports all PCI specific configuration registers
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SDRAM Memory Controller (“SDRAMC”)
The SDRAM Memory Controller has been designed and integrated into the TX7901 processor
to take advantage of high memory bandwidth to external memories. The C790 and the DMA
Controller can both access memory to perform Read / Write operations. The SDRAMC
supports:
•
1 GB memory with four DIMMs (8M
×
8B
×
4) or two double-side DIMMs
(8M
×
8B
×
4
×
2)
•
PC 100/133 DIMM/SO-DIMM
•
Internal PLL for de-skewing clock and data between the TX7901 and SDRAM
DIMMs
•
Four-bank interleaving for 64/128/256 Mb SDRAMs
•
Two-bank interleaving for 16 Mb SDRAMs
•
ECC, single-bit error correction, double-bit error detection
•
Aligned burst transactions
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DMA Controller (“DMAC”)
Eight independent DMA channels have been implemented for external and internal peripherals
that access memory. DMA operation provides the fastest access to memory while the C790
executes in parallel from internal caches. The DMAC supports:
•
Eight independent DMA channels for both internal and external DMA requests
•
Chaining via linked lists of records
•
Block and Slice modes
•
Memory to memory, memory to peripheral, and peripheral to memory transactions