Toshiba TMPR7901, Руководство пользователя

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Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-17
14.5 Special Features
This section discusses how and where the TX7901 UARTs differ from the original
NS16550A device.
14.5.1 Transmit Machine Timing
TXM (Transmit Machine) starts after 2 – 3 baud clock cycles from the time the TX Holding
Register is written. SOUT goes Low 7 – 8 baud clock cycles from the time the TX Holding
Register is written.
14.5.2 THR Empty Interrupt Timing
A TX Holding Register Empty interrupt will be generated 17 – 18 clocks after data have been
written to the TX Holding Register, providing Transmit Machine Was Idle when the data
were written.
If the TX Holding Register is empty when the TX Holding Register Empty interrupt is enabled,
an interrupt will be generated immediately. In the original device, this interrupt is reset on the
falling edge of WR* (Transmit register). In the UART, it is reset on the rising edge of this
signal.
14.5.3 FIFO Reset Timing
When using bits 0 – 3 of the FIFO Control Register to reset the FIFOs, the following timing
restrictions apply:
FCR0 – Both FIFOs are reset by the master reset (MR), and are held unless FCR0 is set to
1.
FCR1 – The RX FIFO clear requires at least one CLK period to complete the reset and clear
itself.
FCR2 – The TX FIFO clear requires at least one CLK period to complete the reset and clear
itself.
14.5.4 Rx Line Status Interrupt Timing
In the original device, the Rx Line Status Interrupt timing is reset on the rising edge of RD*
(Receive register). In the UART, it is reset on the falling edge of this signal.
14.5.5 Timeout interrupt timing
In the original device, the Timeout Interrupt is cleared on the falling edge of RD* (Receive
register). In the UART, it is cleared one half-clock cycle after the rising edge of this signal.