Toshiba TMPR7901, Руководство пользователя

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Chapter 6: SDRAM Memory Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
6-24
sdrDQM[7:0]* outputs. The ECC data are read on the sdrCB[7:0] inputs.
2. Modify the ECC information based on the data that are to be written. The ECC nibble is
modified in the SDRAM Controller.
3. Write the new data and new ECC byte.
Figure 6-8 illustrates the procedure that the SDRAM Controller uses to generate ECC in a
partial write to SDRAM.
Figure 6-8 Read Modify Write Transaction by the SDRAM Controller
1. READ All Data
and Check Bits
2. Modify Check
Byte in TX7901
3. Write New Data and
Modified Check Byte
x72
SDRAM
x8
SDRAM
#1
x8
SDRAM
#2
x8
SDRAM
#7
x8
SDRAM
#8
x8
SDRAM
#9
y
y
y
Data[7:0]
Data[15:8]
Data[55:48]
Data[63:56]
CB[7:0]
SDQM[0]*
ASSERTED
SDQM[1]*
ASSERTED
SDQM[6]*
ASSERTED
SDQM[7]*
ASSERTED
SDQM[X]*
ASSERTED
x72
SDRAM
x8
SDRAM
#1
x8
SDRAM
#2
x8
SDRAM
#7
x8
SDRAM
#8
x8
SDRAM
#9
y
y
y
Data[7:0]
NEW
Data[15:8]
NEW
Data[55:48]
EXISTING
Data[63:56]
EXISTING
CB[7:0]
SDRAM Check
SDQM[0]*
ASSERTED
SDQM[1]*
ASSERTED
SDQM[6]*
ASSERTED
SDQM[7]*
ASSERTED
SDQM[X]*
ASSERTED
Existing Check Bits
X X X X X X X X
Y Y Y Y Y Y Y Y
MODIFIED
Check Bits