Toshiba TMPR7901, Руководство пользователя

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Chapter 7: C790 Bus/G-Bus Bridge
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
7-4
7.5 Bus Errors
Bus errors occur during a bus transaction when no target device responds to the initiator
within a given number of bus cycles. When a bus error occurs, the initiator terminates the
transaction, signals an interrupt to the C790 and records the bad address. The target
device returns to the idle state after a bus error has been detected.
There are two kinds of bus errors. One is a C790 Bus error, and the other is a G-Bus error.
Each bus error has a counter associated with it. When the initiator initiates a transaction,
the counter begins to count down. When the counter counts to zero and there is no
response from any target, a bus error is signaled. Since the C790 Bus Clock is twice as
fast as the G-Bus Clock, we can state the following constraint:
(C790 Bus Counter) < G-Bus Counter
×
2 – n, where n is the maximum latency of G
→
C transfer
This implies that the C790 bus countdown always expires sooner than the G-Bus
countdown if there is any transaction going across the G-Bus bridge (called a “crossing
transaction”.) When there is a crossing transaction, the bridge always passes any C790
bus error to the G-Bus. The initiator or target handles it in the same way a G-Bus error
would be handled.
When a write transaction has posted its data into the FIFO in the bridge, the transaction is
considered “finished”. A write transaction is never a crossing transaction.