Toshiba TMPR7901, Руководство пользователя

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Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-3
14.2.2 Receive Operation
Data are sampled into the RX Shift Register using RCLK. A filter is used to remove spurious
inputs that last for less than two clock periods.
When the complete word has been clocked into the receiver, the data bits are transferred to
the RX Buffer Register or to the RX FIFO (if enabled) to be read by the G-Bus. The receiver
also checks for a stop bit and for correct parity as determined by the Line Control Register.
If enabled, an interrupt will be generated when the data have been transferred to the RX
Buffer Register. Interrupts can also be generated when there is incorrect parity or a missing
stop bit (frame error).
When the FIFOs are enabled, (i.e. Bit 0 of the FIFO Control Register is set), the UART can
store up to 16 bytes of received data at a time. Depending on the selected mode, either
RXRDY or IRQ will go active when the Receive FIFO contains 1, 4, 8, or 14 bytes of data –
to indicate that data are available.
14.2.3 Modem Control Lines
The output Modem Control lines RTS*, DTR*, OUT1*, and OUT2* can be set or cleared by
writing to the Modem Control Register.
The current status of the input Modem Control Lines DCD*, RI*, DSR*, and CTS* can be
read from the Modem Status Register. Bit 2 of this register will be set if the NRI line has
changed from Low to High since the register was last read.
If enabled, an interrupt will be generated when any of the DSR*, CTS*, RI*, or DCD* signals
is asserted.
Note that there are no modem control lines for UART1 due to pin constraints. UART1 is
assumed to use software flow control.
14.3 Interface Signals
Table 14-1 lists the various interface signals for the UARTs.
Table 14-1 Serial I/O Signal Descriptions
SIGNAL TYPE DESCRIPTION
G-Bus Interface
gbsgBusClk Input G-Bus Clock
sysResetB Input G-Bus Reset
gbsgAddr[31:2] Input G-Bus Address Bus
gbsgData[63:0] Input G-Bus Data Bus
gcbgURTRegCSB Input Chip select signal which is generated by the G-Bus Bridge for the UART
gbsgBEB[7:0] Input G-Bus byte enable
gbsgBSize[2:0] Input G-Bus burst transfer size
gbsgRdB Input G-Bus read signal, active Low
gbsgWrB Input G-Bus write signal, active Low
gbsgBurstB Input G-Bus Burst Transaction
gbsgBStartB Input
G-Bus transaction start. The G-Bus Master asserts this signal to indicate the start of a
transaction.