Toshiba TMPR7901, Руководство пользователя

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Chapter 4: Address Maps
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
4-11
The following table is a register map of the individual modules. Please note that this table is
still under construction. See the tables in each relevant chapter for more information.
Name Register Description Address R/W Size(b)
DLM1 Divisor Latch 1 (MS) 0x1E00_8004 R/W 8
IIR1 Interrupt Identification Register 1 0x1E00_8008 R/O 8
FCR1 FIFO Control Register 1 0x1E00_8008 W/O 8
LCR1 Line Control Register 1 0x1E00_800C R/W 8
MCR1 Modem Control Register 1 0x1E00_8010 R/W 8
LSR1 Line Status Register 1 0x1E00_8014 R/O 8
MSR1 Modem Status Register 1 0x1E00_8018 R/W 8
SCR1 Scratch Register 1 0x1E00_801C R/W 8
PSR1 Pre-scaler Register 1 0x1E00_8020 R/W 8
SPI (TSEI) and GPIO Base Address 0x1E00_9000
GPIO_outreg General-purpose I/O Register 0x1E00_9000 R/W 8
GPIO_inreg General-purpose I/O Register 0x1E00_9004 R/O 8
GPIO_outenab General-purpose I/O Register 0x1E00_9008 R/W 8
- Reserved 0x1E00_900C
TSEI_SECR Control Register 0x1E00_9010 R/W 8
TSEI_SESR Status Register 0x1E00_9014 R/W 8
TSEI_SEDR Data Register 0x1E00_9018 R/W 8
TSEI_DDCR Data Direction Register 0x1E00_901C R/W 8
PGB1 (Optional) Base Address 0x1E00_A000
Device & Vendor ID Register 0x1E00_A000 R 32
Status & Command Register 0x1E00_A004 R/W 32
Class Code, Revision ID Register 0x1E00_A008 R 32
BIST, Header Type,
Master Latency Timer & Cache line Size
0x1E00_A00C R/W 32
Memory Base Address[0] 0x1E00_A010 R/W 32
Memory DAC Base Address[0] 0x1E00_A014 R/W 32
Memory Base Address[1] 0x1E00_A018 R/W 32
Memory DAC Base Address[1] 0x1E00_A01C R/W 32
Memory Base Address[2] 0x1E00_A020 R/W 32
Memory DAC Base Address[2] 0x1E00_A024 R/W 32
Reserved 0x1E00_A028
Subsystem ID, Subsystem Vendor ID 0x1E00_A02C R 32
XX,XX,XX,XX 0x1E00_A030 R/W 32
Reserved, 0xDC 0x1E00_A034 R 32
Reserved 0x1E00_A038
Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line 0x1E00_A03C R 32
Reserved, Retry Time Value, TRDY Timeout 0x1E00_A040 R/W 32
I/O Base Address [0] 0x1E00_A044 R/W 32
Reserved 0x1E00_A048 – 0x1E00_A0D8
Pre-existing features, 0xE401 0x1E00_A0DC R/W 32
Pre-existing features 0x1E00_A0E0 R/W 32
Reserved, p2gBase3[35:32], 0x0002 0x1E00_A0E4 R/W 32
p2gBase3[31:0] 0x1E00_A0E8 R/W 32
PCI1
Configuration
Space
Reserved 0x1E00_A0EC - 0x1E00_A0FF
pgbCSR PGB Control and Status Register 0x1E00_A100 R/W 64
g2pLower0 g2pwindow Lower Address Register 0 0x1E00_A108 R/W 64
g2pUpper0 g2pwindow Upper Address Register 0 0x1E00_A110 R/W 64
g2pLower1 g2pwindow Lower Address Register 1 0x1E00_A118 R/W 64